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ADSP-2184N Datasheet

  • ADSP-2184N

  • Analog Devices [DSP Microcomputer]

  • 1458.04KB

  • AD

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ADSP-218xN Series
The EZ-KIT Lite includes the following features:
鈥?75 MHz ADSP-2189M
鈥?Full 16-Bit Stereo Audio I/O with AD73322 Codec
鈥?RS-232 Interface
鈥?EZ-ICE Connector for Emulator Control
鈥?DSP Demonstration Programs
鈥?Evaluation Suite of VisualDSP++
The ADSP-218x EZ-ICE
庐
Emulator provides an easier and
more cost-effective method for engineers to develop and
optimize DSP systems, shortening product development
cycles for faster time-to-market. ADSP-218xN series
members integrate on-chip emulation support with a 14-pin
ICE-Port interface. This interface provides a simpler target
board connection that requires fewer mechanical clearance
considerations than other ADSP-2100 Family EZ-ICEs.
ADSP-218xN series members need not be removed from
the target system when using the EZ-ICE, nor are any adapt-
ers needed. Due to the small footprint of the EZ-ICE con-
nector, emulation can be supported in final board
designs.The EZ-ICE performs a full range of functions,
including:
鈥?In-target operation
鈥?Up to 20 breakpoints
鈥?Single-step or full-speed operation
鈥?Registers and memory values can be examined
and altered
鈥?PC upload and download functions
鈥?Instruction-level emulation of program booting
and execution
鈥?Complete assembly and disassembly of instructions
鈥?C source-level debugging
Additional Information
units process 16-bit data directly and have provisions to
support multiprecision computations. The ALU performs
a standard set of arithmetic and logic operations; division
primitives are also supported. The MAC performs single-
cycle multiply, multiply/add, and multiply/subtract opera-
tions with 40 bits of accumulation. The shifter performs
logical and arithmetic shifts, normalization, denormaliza-
tion, and derive exponent operations.
The shifter can be used to efficiently implement numeric
format control, including multiword and block floating-
point representations.
The internal result (R) bus connects the computational
units so that the output of any unit may be the input of any
unit on the next cycle.
A powerful program sequencer and two dedicated data
address generators ensure efficient delivery of operands to
these computational units. The sequencer supports condi-
tional jumps, subroutine calls, and returns in a single cycle.
With internal loop counters and loop stacks, ADSP-218xN
series members execute looped code with zero overhead; no
explicit jump instructions are required to maintain loops.
Two data address generators (DAGs) provide addresses for
simultaneous dual operand fetches (from data memory and
program memory). Each DAG maintains and updates four
address pointers. Whenever the pointer is used to access
data (indirect addressing), it is post-modified by the value
of one of four possible modify registers. A length value may
be associated with each pointer to implement automatic
modulo addressing for circular buffers.
Five internal buses provide efficient data transfer:
鈥?Program Memory Address (PMA) Bus
鈥?Program Memory Data (PMD) Bus
鈥?Data Memory Address (DMA) Bus
鈥?Data Memory Data (DMD) Bus
鈥?Result (R) Bus
The two address buses (PMA and DMA) share a single
external address bus, allowing memory to be expanded off-
chip, and the two data buses (PMD and DMD) share a
single external data bus. Byte memory space and I/O
memory space also share the external buses.
Program memory can store both instructions and data, per-
mitting ADSP-218xN series members to fetch two oper-
ands in a single cycle, one from program memory and one
from data memory. ADSP-218xN series members can fetch
an operand from program memory and the next instruction
in the same cycle.
In lieu of the address and data bus for external memory
connection, ADSP-218xN series members may be config-
ured for 16-bit Internal DMA port (IDMA port) connec-
tion to external systems. The IDMA port is made up of 16
This data sheet provides a general overview of ADSP-
218xN series functionality. For additional information on
the architecture and instruction set of the processor, refer
to the
ADSP-218x DSP Hardware Reference
and the
ADSP-
218x DSP Instruction Set Reference.
ARCHITECTURE OVERVIEW
The ADSP-218xN series instruction set provides flexible
data moves and multifunction (one or two data moves with
a computation) instructions. Every instruction can be exe-
cuted in a single processor cycle. The ADSP-218xN assem-
bly language uses an algebraic syntax for ease of coding and
readability. A comprehensive set of development tools sup-
ports program development.
The functional block diagram is an overall block diagram of
the ADSP-218xN series. The processor contains three in-
dependent computational units: the ALU, the multiplier/
accumulator (MAC), and the shifter. The computational
EZ-ICE is a registered trademark of Analog Devices, Inc.
REV. 0
鈥?鈥?/div>

ADSP-2184N PDF文件相关型号

ADSP-2185NKCA-320,ADSP-2186NKCA-320,ADSP-2187N,ADSP-2188N,ADSP-2189N

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