PRELIMINARY
against inadvertent writes (refer to Table 5 for com-
mand definitions). In addition, the following hardware
data protection measures prevent accidental erasure
or programming, which might otherwise be caused by
spurious system level signals during V
CC
power-up
and power-down transitions, or from system noise.
Low V
CC
Write Inhibit
Perform Erase or
Program Operations
START
RESET# = V
ID
(Note 1)
RESET# = V
IH
Temporary Sector
Unprotect Completed
(Note 2)
When V
CC
is less than V
LKO
, the device does not ac-
cept any write cycles. This protects data during V
CC
power-up and power-down. The command register and
all internal program/erase circuits are disabled, and the
device resets. Subsequent writes are ignored until V
CC
is greater than V
LKO
. The system must provide the
proper signals to the control pins to prevent uninten-
tional writes when V
CC
is greater than V
LKO
.
Write Pulse 鈥淕litch鈥?Protection
Noise pulses of less than 5 ns (typical) on OE#, CE# or
WE# do not initiate a write cycle.
20514C-5
Logical Inhibit
Write cycles are inhibited by holding any one of OE# =
V
IL
, CE# = V
IH
or WE# = V
IH
. To initiate a write cycle,
CE# and WE# must be a logical zero while OE# is a
logical one.
Power-Up Write Inhibit
If WE# = CE# = V
IL
and OE# = V
IH
during power up, the
device does not accept commands on the rising edge
of WE#. The internal state machine is automatically
reset to reading array data on power-up.
Notes:
1. All protected sectors unprotected.
2. All previously protected sectors are protected once
again.
Figure 1.
Temporary Sector Unprotect Operation
Hardware Data Protection
The command sequence requirement of unlock cycles
for programming or erasing provides data protection
Am29LV400
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