Am29LV400B-120SCB Datasheet

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Am29LV400B-120SCB
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Advanced Micro Devices [4 Megabit (512 K x 8-Bit/256 K x 16...
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PRELIMINARY

The remaining scenario is that the system initially de-

termines that the toggle bit is toggling and DQ5 has not

gone high. The system may continue to monitor the

toggle bit and DQ5 through successive read cycles, de-

termining the status as described in the previous para-

graph. Alternatively, it may choose to perform other

system tasks. In this case, the system must start at the

beginning of the algorithm when it returns to determine

the status of the operation (top of Figure 5).

START

Read DQ7鈥揇Q0

(Note 1)

Read DQ7鈥揇Q0

DQ5: Exceeded Timing Limits

DQ5 indicates whether the program or erase time has

exceeded a specified internal pulse count limit. Under

these conditions DQ5 produces a 鈥?.鈥?This is a failure

condition that indicates the program or erase cycle was

not successfully completed.

The DQ5 failure condition may appear if the system

tries to program a 鈥?鈥?to a location that is previously

programmed to 鈥?.鈥?/div>

Only an erase operation can

change a 鈥?鈥?back to a 鈥?.鈥?/div>

Under this condition, the

device halts the operation, and when the operation has

exceeded the timing limits, DQ5 produces a 鈥?.鈥?/div>

Under both these conditions, the system must issue

the reset command to return the device to reading

array data.

Toggle Bit

= Toggle?

Yes

DQ5 = 1?

Yes

Read DQ7鈥揇Q0

Twice

(Notes

1, 2)

DQ3: Sector Erase Timer

After writing a sector erase command sequence, the

system may read DQ3 to determine whether or not an

erase operation has begun. (The sector erase timer

does not apply to the chip erase command.) If addi-

tional sectors are selected for erasure, the entire time-

out also applies after each additional sector erase com-

mand. When the time-out is complete, DQ3 switches

from 鈥?鈥?to 鈥?.鈥?If the time between additional sector

erase commands from the system can be assumed to

be less than 50

碌s,

the system need not monitor DQ3.

See also the 鈥淪ector Erase Command Sequence鈥?sec-

tion.

After the sector erase command sequence is written,

the system should read the status on DQ7 (Data# Poll-

ing) or DQ6 (Toggle Bit I) to ensure the device has ac-

cepted the command sequence, and then read DQ3. If

DQ3 is 鈥?鈥? the internally controlled erase cycle has be-

gun; all further commands (other than Erase Suspend)

are ignored until the erase operation is complete. If

DQ3 is 鈥?鈥? the device will accept additional sector

erase commands. To ensure the command has been

accepted, the system software should check the status

of DQ3 prior to and following each subsequent sector

erase command. If DQ3 is high on the second status

check, the last command might not have been ac-

cepted. Table 6 shows the outputs for DQ3.

Toggle Bit

= Toggle?

Yes

Program/Erase

Operation Not

Complete, Write

Reset Command

Program/Erase

Operation Complete

Notes:

1. Read toggle bit twice to determine whether or not it is

toggling. See text.

2. Recheck toggle bit because it may stop toggling as DQ5

changes to 鈥?鈥?. See text.

20514C-9

Figure 5.

Toggle Bit Algorithm

Am29LV400

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