Am29LV400B-120SCB Datasheet

IC型号：
Am29LV400B-120SCB
PDF描述：
Advanced Micro Devices [4 Megabit (512 K x 8-Bit/256 K x 16...
文件大小：
483.89KB
芯片厂家：
AMD

阅览下载纠错 0

扫码查看芯片数据手册

上传产品规格书

PDF预览

PRELIMINARY

COMMAND DEFINITIONS

Writing specific address and data commands or se-

quences into the command register initiates device op-

erations. Table 5 defines the valid register command

sequences. Writing

incorrect address and data val-

ues

or writing them in the

improper sequence

resets

the device to reading array data.

All addresses are latched on the falling edge of WE# or

CE#, whichever happens later. All data is latched on

the rising edge of WE# or CE#, whichever happens

first. Refer to the appropriate timing diagrams in the

鈥淎C Characteristics鈥?section.

The reset command may be written between the se-

quence cycles in an autoselect command sequence.

Once in the autoselect mode, the reset command

must

be written to return to reading array data (also applies

to autoselect during Erase Suspend).

If DQ5 goes high during a program or erase operation,

writing the reset command returns the device to read-

ing array data (also applies during Erase Suspend).

See 鈥淎C Characteristics鈥?for parameters, and to Figure

13 for the timing diagram.

Reading Array Data

The device is automatically set to reading array data

after device power-up. No commands are required to

retrieve data. The device is also ready to read array

data after completing an Embedded Program or Em-

bedded Erase algorithm.

After the device accepts an Erase Suspend command,

the device enters the Erase Suspend mode. The sys-

tem can read array data using the standard read tim-

ings, except that if it reads at an address within erase-

suspended sectors, the device outputs status data.

After completing a programming operation in the Erase

Suspend mode, the system may once again read array

data with the same exception. See 鈥淓rase Sus-

pend/Erase Resume Commands鈥?for more information

on this mode.

The system

must

issue the reset command to re-ena-

ble the device for reading array data if DQ5 goes high,

or while in the autoselect mode. See the 鈥淩eset Com-

mand鈥?section, next.

See also 鈥淩equirements for Reading Array Data鈥?in the

鈥淒evice Bus Operations鈥?section for more information.

The Read Operations table provides the read parame-

ters, and Figure 12 shows the timing diagram.

Autoselect Command Sequence

The autoselect command sequence allows the host

system to access the manufacturer and devices codes,

and determine whether or not a sector is protected.

Table 5 shows the address and data requirements.

This method is an alternative to that shown in Table 4,

which is intended for PROM programmers and requires

on address bit A9.

The autoselect command sequence is initiated by writ-

ing two unlock cycles, followed by the autoselect com-

mand. The device then enters the autoselect mode,

and the system may read at any address any number

of times, without initiating another command sequence.

A read cycle at address XX00h retrieves the manufac-

turer code. A read cycle at address XX01h in word

mode (or 02h in byte mode) returns the device code. A

read cycle containing a sector address (SA) and the

address 02h in word mode (or 04h in byte mode) re-

turns 01h if that sector is protected, or 00h if it is unpro-

tected. Refer to Tables 2 and 3 for valid sector

addresses.

The system must write the reset command to exit the

autoselect mode and return to reading array data.

Word/Byte Program Command Sequence

The system may program the device by word or byte,

depending on the state of the BYTE# pin. Program-

ming is a four-bus-cycle operation. The program com-

mand sequence is initiated by writing two unlock write

cycles, followed by the program set-up command. The

program address and data are written next, which in

turn initiate the Embedded Program algorithm. The

system is

not

required to provide further controls or tim-

ings. The device automatically generates the program

pulses and verifies the programmed cell margin. Table

5 shows the address and data requirements for the

byte program command sequence.

When the Embedded Program algorithm is complete,

the device then returns to reading array data and ad-

dresses are no longer latched. The system can deter-

mine the status of the program operation by using

DQ7, DQ6, or RY/BY#. See 鈥淲rite Operation Status鈥?/div>

for information on these status bits.

Reset Command

Writing the reset command to the device resets the de-

vice to reading array data. Address bits are don鈥檛 care

for this command.

The reset command may be written between the se-

quence cycles in an erase command sequence before

erasing begins. This resets the device to reading array

data. Once erasure begins, however, the device ig-

nores reset commands until the operation is complete.

The reset command may be written between the se-

quence cycles in a program command sequence be-

fore programming begins. This resets the device to

reading array data (also applies to programming in

Erase Suspend mode). Once programming begins,

however, the device ignores reset commands until the

operation is complete.

Am29LV400

prev next

Am29LV400B-120SCB PDF文件相关型号

Am29LV400B-90REC,Am29LV400B-90REE,Am29LV400B-90REI,Am29LV400B-90RFC,Am29LV400B-90RFE,Am29LV400B-90RFI,Am29LV400T-150SE,Am29LV400T-150SI,Am29LV400T-150SIB,Am29LV400T-90REC,Am29LV400T-90RECB,Am29LV400T-90REE,Am29LV400T-90RFE

Am29LV400B-120SCB相关型号PDF文件下载

型号

版本

描述

厂商

下载
AM290

英文版

Analog IC

ETC

AM290
AM291

英文版

Analog IC

ETC

AM291
AM292

英文版

Analog IC

ETC

AM292
AM2904

英文版

A High-Performance 8-Bit Slice Microprogram Sequencer

AMD

AM2904
AM2904

英文版

A High-Performance 8-Bit Slice Microprogram Sequencer

AMD [Advan...

AM2904
AM2914

英文版

Eight-Bit AM29116 I/O Support

AMD

AM2914
AM2914

英文版

Eight-Bit AM29116 I/O Support

AMD [Advan...

AM2914
AM2918

英文版

MICROPROGRAM SEQUENCER BLOCK DIAGRAM

AMD

AM2918
AM2918

英文版

MICROPROGRAM SEQUENCER BLOCK DIAGRAM

AMD [Advan...

AM2918
AM2922

英文版

Eight Input multiplexer with Control Register

AMD

AM2922
AM2922

英文版

Eight Input multiplexer with Control Register

AMD [Advan...

AM2922
AM2925

英文版

A High-Performance 8-Bit Slice Microprogram Sequencer

AMD

AM2925
AM2925

英文版

A High-Performance 8-Bit Slice Microprogram Sequencer

AMD [Advan...

AM2925
AM2940

英文版

DMA ADDRESS GENERATOR

ETC

AM2940
AM2940

英文版

A High-Performance 8-Bit Slice Microprogram Sequencer

AMD

AM2940
AM2940

英文版

DMA ADDRESS GENERATOR

ETC [ETC]

AM2940
AM2942

英文版

A High-Performance 8-Bit Slice Microprogram Sequencer

AMD

AM2942
AM2942

英文版

A High-Performance 8-Bit Slice Microprogram Sequencer

AMD [Advan...

AM2942
AM2946

英文版

Octal Three-State Bidirectional Bus Transceiver

ETC

AM2946
AM2946

英文版

Octal Three-State Bidirectional Bus Transceiver

ETC [ETC]

AM2946

Am29LV400B-120SCB Datasheet

PDF预览

Am29LV400B-120SCB PDF文件相关型号

Am29LV400B-120SCB相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

Am29LV400B-120SCB Datasheet

PDF预览

Am29LV400B-120SCB PDF文件相关型号

Am29LV400B-120SCB相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

建议反馈

PDF纠错X