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CS5530 Datasheet

  • CS5530

  • National Semiconductor [Geode⑩ CS5530 I/O Companion Multi-...

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Geode鈩?CS5530
Signal Definitions
(Continued)
2.2
2.2.1
SIGNAL DESCRIPTIONS
Reset Interface
Pin
No.
C14
Type
O
Description
PCI Reset
PCI_RST# resets the PCI bus and is asserted while POR# is asserted,
and for approximately 9 ms following the deassertion of POR#.
Signal Name
PCI_RST#
POR#
K24
I
smt
Power On Reset
POR# is the system reset signal generated from the power supply to indi-
cate that the system should be reset.
CPU Reset
CPU_RST resets the CPU and is asserted while POR# is asserted, and
for approximately 9 ms following the deassertion of POR#.
CPU_RST
K25
O
2.2.2
Clock Interface
Pin
No.
J26
Type
I
Description
PCI Clock
The PCI clock is used to drive most circuitry of the CS5530.
Signal Name
PCICLK
TVCLK
B2
I
5VT
Television Clock
The TVCLK is an input from a digital NTSC/PAL converter which is option-
ally re-driven back out onto the DCLK signal under software program con-
trol. This is only used if interfacing to a compatible digital NTSC/PAL
encoder device.
DOT Clock
DOT clock is generated by the CS5530 and typically connects to the pro-
cessor to create the video pixel clock. The minimum frequency of DCLK is
10 MHz and the maximum is 200 MHz.
DCLK
A10
O
ISACLK
AD6
O
ISA Bus Clock
ISACLK is derived from PCICLK and is typically programmed for approxi-
mately 8 MHz. F0 Index 50h[2:0] is used to program the ISA clock divisor.
CLK_14MHZ
P24
I
14.31818 MHz Clock
DOT clock (DCLK) is derived from this clock.
USBCLK
W1
I
USBCLK
This input is used as the clock source for the USB. In this mode, a 48 MHz
clock source input is required.
CLK_32K
AE3
I/O
5VT
32KHz Clock
CLK_32K is a 32.768 KHz clock used to generate reset signals, as well as
to maintain power management functionality. It should be active when
power is applied to the CS5530.
CLK_32K can be an input or an output. As an output CLK_32K is inter-
nally derived from CLK_14MHZ. F0 Index 44h[5:4] are used to program
this pin.
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