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CS5530 Datasheet

  • CS5530

  • National Semiconductor [Geode⑩ CS5530 I/O Companion Multi-...

  • 3339.45KB

  • NSC

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Geode鈩?CS5530
Signal Definitions
(Continued)
2.2.3
CPU Interface (Continued)
Pin
No.
L24
Type
I/O
Description
Suspend 3 Volt Active
SUSP_3V can be connected to the output enable (OE) of a clock synthe-
sis or buffer chip to stop the clocks to the system. SUSP_3V is asserted
on any write to Suspend Notebook Command Register (F0 Index AFh)
with bit 0 set in the Clock Stop Control Register (F0 Index BCh).
SUSP_3V is only asserted after the SUSP#/SUSPA# handshake.
As an input, SUSP_3V is sampled during power-on-reset to determine the
inactive state. This allows the system designer to match the active state of
SUSP_3V to the inactive state for a clock driver output enabled with a pull-
up/down 10-kohm resistor. If pulled down, SUSP_3V is active high. If
pulled up, SUSP_3V is active low.
Signal Name
SUSP_3V
2.2.4
PCI Interface
Pin
No.
Refer
to Table
2-3
Type
I/O
t/s
5VT
Description
PCI Address/Data
AD[31:0] is a physical address during the first clock of a PCI transaction; it
is the data during subsequent clocks.
When the CS5530 is a PCI master, AD[31:0] are outputs during the
address and write data phases, and are inputs during the read data phase
of a transaction.
When the CS5530 is a PCI slave, AD[31:0] are inputs during the address
and write data phases, and are outputs during the read data phase of a
transaction.
Signal Name
AD[31:0]
C/BE[3:0]#
D26,
A24,
B21,
B18
I/O
t/s
5VT
PCI Bus Command and Byte Enables
During the address phase of a PCI transaction, C/BE[3:0]# defines the
bus command. During the data phase of a transaction, C/BE[3:0]# are the
data byte enables.
C/BE[3:0]# are outputs when the CS5530 is a PCI master and are inputs
when it is a PCI slave.
INTA#,
INTB#,
INTC#,
INTD#
A14,
D15,
C15,
B14
I
5VT
PCI Interrupt Pins
The CS5530 provides inputs for the optional 鈥渓evel-sensitive鈥?PCI inter-
rupts (also known in industry terms as PIRQx#). These interrupts may be
mapped to IRQs of the internal 8259s using PCI Interrupt Steering Regis-
ters 1 and 2 (F0 Index 5Ch and 5Dh).
The USB controller uses INTA# as its output signal. Refer to PCIUSB
Index 3Dh.
REQ#
J25
O
5VT
PCI Bus Request
The CS5530 asserts REQ# in response to a DMA request or ISA master
request to gain ownership of the PCI bus. The REQ# and GNT# signals
are used to arbitrate for the PCI bus.
REQ# should connect to the REQ0# of the GXLV processor and function
as the highest-priority PCI master.
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24
Revision 4.1

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