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CS5530 Datasheet

  • CS5530

  • National Semiconductor [Geode⑩ CS5530 I/O Companion Multi-...

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  • NSC

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Geode鈩?CS5530
Functional Description
(Continued)
3.1
PROCESSOR INTERFACE
The CS5530 interface to the GXLV processor consists of
seven miscellaneous connections, the PCI bus interface
signals, plus the display controller connections. Figure 3-1
shows the interface requirements. Note that the PC/AT
legacy pins NMI, WM_RST, and A20M are all virtual func-
tions executed in SMM (System Management Mode) by
the BIOS.
鈥?PSERIAL is a one-way serial bus from the processor to
the CS5530 used to communicate power-management
states and VSYNC information for VGA emulation.
鈥?IRQ13 is an input from the processor indicating that a
floating point error was detected and that INTR should
be asserted.
鈥?INTR is the level output from the integrated 8259 PICs
and is asserted if an unmasked interrupt request
(IRQn) is sampled active.
鈥?SMI# is a level-sensitive interrupt to the processor that
can be configured to assert on a number of different
system events. After an SMI# assertion, SMM is
entered and program execution begins at the base of
the SMM address space. Once asserted, SMI#
remains active until the SMI source is cleared.
鈥?SUSP# and SUSPA# are handshake pins for imple-
menting CPU Clock Stop and clock throttling.
鈥?CPU_RST resets the CPU and is asserted for approxi-
mately 9 ms after the negation of POR#.
鈥?PCI bus interface signals.
鈥?Display subsystem interface connections.
PIXEL[23:0]
Geode鈩?CS5530
I/O Companion
PSERIAL
IRQ13
INTR
SMI#
SUSP#
SUSPA#
CPU_RST
AD[31:0]
C/BE[3:0]#
PAR
FRAME#
IRDY#
TRDY#
STOP#
LOCK#
DEVSEL#
PERR#
SERR#
REQ#
GNT#
PCLK
DCLK
HSYNC
VSYNC
FP_HSYNC
FP_VSYNC
ENA_DISP
VID_VAL
VID_CLK
VID_DATA[7:0]
VID_RDY
Note
Geode鈩?GXLV
Processor
SERIALP
IRQ13
INTR
SMI#
SUSP#
SUSPA#
RESET
AD[31:0]
C/BE[3:0]#
PAR
FRAME#
IRDY#
TRDY#
STOP#
LOCK#
DEVSEL#
PERR#
SERR#
REQ0#
GNT0#
PCLK
DCLK
CRT_HSYNC
CRT_VSYNC
FP_HSYNC
FP_VSYNC
ENA_DISP
VID_VAL
VID_CLK
VID_DATA[7:0]
VID_RDY
PIXEL[17:0]
Note:
Refer to Figure 3-3 for correct interconnection
of PIXEL lines with the processor.
Figure 3-1. Processor Signal Connections
Revision 4.1
41
www.national.com

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