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CS5530 Datasheet

  • CS5530

  • National Semiconductor [Geode⑩ CS5530 I/O Companion Multi-...

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Geode鈩?CS5530
Functional Description
(Continued)
3.4
POWER MANAGEMENT
address register in Function 1 (F1) at Index 10h (F1BAR).
F1BAR sets the base address for the SMI status and
ACPI timer support registers as shown in Table 3-11.
3.4.1 APM Support
Many notebook computers rely solely on an APM
(Advanced Power Management) driver for enabling the
operating system to power-manage the CPU. APM pro-
vides several services which enhance the system power
management and is theoretically the best approach; but in
its current form, APM is imperfect for the following rea-
sons:
鈥?APM is an OS-specific driver, and may not be available
for some operating systems.
鈥?Application support is inconsistent. Some applications
in foreground may prevent Idle calls.
鈥?APM does not help with Suspend determination or
peripheral power management.
The CS5530 provides two entry points for APM support:
鈥?Software CPU Suspend control via the CPU Suspend
Command Register (F0 Index AEh)
鈥?Software SMI entry via the Software SMI Register (F0
Index D0h). This allows the APM BIOS to be part of the
SMI handler.
These registers are shown in Table 3-12.
The power management resources provided by a com-
bined CS5530/GXLV processor based system supports a
full-featured notebook implementation. The following
explanations pertain to a full-featured 鈥渘otebook鈥?power
management system. The extent to which these
resources are employed depends on the application and
on the discretion of the system designer.
Power management resources can be grouped according
to the function they enable or support. The major func-
tions are as follows:
鈥?APM Support
鈥?CPU Power Management
- Suspend Modulation
- 3 Volt Suspend
- Save-to-Disk
鈥?Peripheral Power Management
- Device Idle Timers and Traps
- General Purpose Timers
- ACPI Timer Register
- General Purpose I/O Pins
- Power Management SMI Status Reporting Registers
Included in the following subsections are details regarding
the registers used for configuring power management fea-
tures. The majority of these registers are directly
accessed through the PCI configuration register space
designated as Function 0 (F0). However, included in the
discussions are references to F1BAR+Memory Offset
xxh. This refers to the registers accessed through a base
Table 3-11. Base Address Register (F1BAR) for SMI Status and ACPI Timer Support
Bit
Description
Base Address Register - F1BAR (R/W)
Reset Value = 00000000h
F1 Index 10h-13h
This register sets the base address of the memory mapped SMI status and ACPI timer related registers. Bits [7:0] are read only (00h),
indicating a 256 byte memory address range. Refer to Table 4-16 for the SMI status and ACPI timer registers bit formats and reset val-
ues. The upper 16 bytes are always mapped to the ACPI timer, and are always memory mapped.
Note:
In Silicon Revision 1.3 and above the ACPI Timer Count Register is accessible through I/O Port 121Ch.
31:8
7:0
SMI Status/Power Management Base Address
Address Range (Read Only)
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54
Revision 4.1

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