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CS8404A-CS Datasheet

  • CS8404A-CS

  • Cirrus Logic [96KHZ DIGITAL AUDIO TRANSMITTER]

  • 358.44KB

  • CIRRUS

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CS8403A CS8404A
7
X:00
6
5
4
3
2
1
0
A
D
D
R
E
S
S
0
Status register 0
1
Control Register 1
Control Register 2
2
Control Register 3
3
4
5
User Data
6
7
8
1st Four
1st Four 1st Four
9
Bytes of
Bytes of Bytes of
Left C. S.
A
C.S. Data C.S. Data
Data
B
C
D
C. S.
Left C. S.
Data
Data
E
F
10
1st Four
Bytes of
11
Right
12
C. S.
13
Data
Last 20
14
Bytes
Right
15 Channel
C. S.
16 Status
Data
Auxiliary
17
Data
Data
18
19
1A
1B
1C
1D
1E
1F
0
1
2
Memory Mode
Figure 5. CS8403A Buffer Memory Modes
FLAG2 FLAG1 FLAG0
FLAG2:
FLAG1:
FLAG0:
High for first four bytes of channel status
Memory mode dependent - See Figure 11
High for last two bytes of user data
Figure 6. Status Register
7
X:01
6
5
4
3
2
1
0
BKST TRNPT
MASK2 MASK1 MASK0
U
N
D
E
F
I
N
E
D
BKST:
Causes realignment of data block when set to 鈥?鈥?/div>
TRNPT: Selects Transparent Mode appropriatley setting data delay
through device
MASK2: Interrupt mask for FLAG2. A 鈥?鈥?enables the interrupt.
MASK1: Interrupt mask for FLAG1.
MASK0: Interrupt mask for FLAG0.
Figure 7. Control Register 1
7
X:02
M1
6
M0
5
V
4
B1
3
B0
2
CRCE
1
MUTE
0
RST
M1:
M0:
V:
B1:
B0:
CRCE:
MUTE:
RST:
with M0, selects MCK frequency.
with M1, selects MCK frequency.
Validity bit of current sample.
with B0, selects the buffer memory mode
with B1, selects the buffer memory mode
Channel status CRC Enable. Professional mode only.
When clear, transmitted audio data is set to zero.
When clear, drivers are disabled, frame counters cleared.
Figure 8. Control Register 2
M1
0
0
3
1
1
M0
0
1
0
1
MCLK
128x Input Word Rate
192x Input Word Rate
256x Input Word Rate
384x Input Word Rate
Table 1. MCLK Frequencies
B0 select one of three modes for the buffer memo-
ry. The different modes are shown in Figure 5 and
the bit combinations in Table 2. More information
on the different modes can be found in the
Buffer
Memory
section. Bit 2, CRCE, is the channel sta-
tus CRCC enable and should only be used in pro-
fessional mode. When CRCE is high, the channel
status data cyclic redundancy check characters are
10
B1
0
0
1
1
B0
0
1
0
1
Mode
0
1
2
3
Buffer Memory Contents
Channel Status
Auxiliary Data
Independent Channel Status
Reserved
Table 2. Buffer Memory Modes
DS239PP1

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