LTAEZ Datasheet

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LTAEZ
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Linear Integrated Systems [Differential Input 16-Bit No Lat...
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LTC2433-1

APPLICATIO S I FOR ATIO

Bit 18 (first output bit) is the end of conversion (EOC)

indicator. This bit is available at the SDO pin during the

conversion and sleep states whenever the CS pin is LOW.

This bit is HIGH during the conversion and goes LOW

when the conversion is complete.

Bit 17 (second output bit) is a dummy bit (DMY) and is

always LOW.

Bit 16 (third output bit) is the conversion result sign indi-

cator (SIG). If V

is >0, this bit is HIGH. If V

is <0, this

bit is LOW.

Bit 15 (fourth output bit) is the most significant bit (MSB)

of the result. This bit in conjunction with Bit 16 also

provides the underrange or overrange indication. If both

Bit 16 and Bit 15 are HIGH, the differential input voltage is

above +FS. If both Bit 16 and Bit 15 are LOW, the

differential input voltage is below 鈥揊S.

The function of these bits is summarized in Table 1.

Table 1. LTC2433-1 Status Bits

Input Range

鈮?/div>

0.5 鈥?V

REF

鈮?/div>

< 0.5 鈥?V

REF

鈥?.5 鈥?V

REF

鈮?/div>

< 0V

< 鈥?0.5 鈥?V

REF

Bit 18 Bit 17 Bit 16 Bit 15

EOC DMY SIG MSB

Bits 15-0 are the 16-Bit conversion result MSB first.

Bit 0 is the least significant bit (LSB).

Data is shifted out of the SDO pin under control of the serial

clock (SCK), see Figure 3. Whenever CS is HIGH, SDO

remains high impedance and any externally generated

BIT 18

SDO

Hi-Z

EOC

BIT 17

鈥淥鈥?/div>

BIT 16

SIG

SCK

SLEEP

Figure 3. Output Data Timing

24331fa

SCK clock pulses are ignored by the internal data out shift

In order to shift the conversion result out of the device, CS

must first be driven LOW. EOC is seen at the SDO pin of the

device once CS is pulled LOW. EOC changes real time from

HIGH to LOW at the completion of a conversion. This

signal may be used as an interrupt for an external micro-

controller. Bit 18 (EOC) can be captured on the first rising

edge of SCK. Bit 17 is shifted out of the device on the first

falling edge of SCK. The final data bit (Bit 0) is shifted out

on the falling edge of the 18th SCK and may be latched on

the rising edge of the 19th SCK pulse. On the falling edge

of the 19th SCK pulse, SDO goes HIGH indicating the

initiation of a new conversion cycle. This bit serves as EOC

(Bit 18) for the next conversion cycle. Table 2 summarizes

the output data format.

In order to remain compatible with some SPI

microcontrollers, more than 19 SCK clock pulses may be

applied. As long as these clock edges are complete before

the conversion ends, they will not effect the serial data.

However, switching SCK during a conversion may gener-

ate ground currents in the device leading to extra offset

and noise error sources.

As long as the voltage on the analog input pins is main-

tained within the 鈥?0.3V to (V

+ 0.3V) absolute maximum

operating range, a conversion result is generated for any

differential input voltage V

from 鈥揊S = 鈥?.5 鈥?V

REF

+FS = 0.5 鈥?V

REF

. For differential input voltages greater than

+FS, the conversion result is clamped to the value corre-

sponding to the +FS + 1LSB. For differential input voltages

below 鈥揊S, the conversion result is clamped to the value

corresponding to 鈥揊S 鈥?1LSB.

BIT 15

MSB

BIT 14

BIT 1

BIT 0

LSB

CONVERSION

24331 F03

U U

DATA OUTPUT

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