LTAEZ Datasheet

  • LTAEZ

  • Linear Integrated Systems [Differential Input 16-Bit No Lat...

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  • LINEAR

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LTC2433-1
APPLICATIO S I FOR ATIO
The serial data output pin (SDO) is Hi-Z as long as CS is
HIGH. At any time during the conversion cycle, CS may be
pulled LOW in order to monitor the state of the converter.
While CS is pulled LOW, EOC is output to the SDO pin.
EOC = 1 while a conversion is in progress and EOC = 0 if
the device is in the sleep state. With CS high, the device
automatically enters the low power sleep state once the
conversion is complete.
When the device is in the sleep state (EOC = 0), its
conversion result is held in an internal static shift regis-
ter. Data is shifted out the SDO pin on each falling edge of
SCK. This enables external circuitry to latch the output on
the rising edge of SCK. EOC can be latched on the first
rising edge of SCK and the last bit of the conversion result
can be latched on the 19th rising edge of SCK. On the 19th
falling edge of SCK, the device begins a new conversion.
2.7V TO 5.5V
1碌F
1
ANALOG INPUT RANGE
鈥?.5V
REF
TO 0.5V
REF
CS
TEST EOC
TEST EOC
BIT 0
SDO
EOC
Hi-Z
Hi-Z
Hi-Z
SCK
(EXTERNAL)
SLEEP
DATA
OUTPUT
CONVERSION
SLEEP
DATA OUTPUT
SLEEP
CONVERSION
24331 F07
TEST EOC (OPTIONAL)
Figure 7. External Serial Clock, Reduced Data Output Length
14
U
SDO goes HIGH (EOC = 1) indicating a conversion is in
progress.
At the conclusion of the data cycle, CS may remain LOW
and EOC monitored as an end-of-conversion interrupt.
Alternatively, CS may be driven HIGH setting SDO to Hi-Z.
As described above, CS may be pulled LOW at any time in
order to monitor the conversion status.
Typically, CS remains LOW during the data output state.
However, the data output state may be aborted by pulling
CS HIGH anytime between the first rising edge and the
19th falling edge of SCK, see Figure 7. On the rising edge
of CS, the device aborts the data output state and imme-
diately initiates a new conversion. This is useful for abort-
ing an invalid conversion cycle or synchronizing the start
of a conversion.
V
CC
F
O
10
= EXTERNAL CLOCK SOURCE
= INTERNAL OSC/SIMULTANEOUS
50Hz/60Hz REJECTION
LTC2433-1
REFERENCE
VOLTAGE
0.1V TO V
CC
2
3
4
5
6
REF
+
REF
鈥?/div>
IN
IN
+
鈥?/div>
W
U U
SCK
9
3-WIRE
SPI INTERFACE
SDO
CS
8
7
GND
BIT 18
EOC
BIT 17
鈥淥鈥?/div>
BIT 16
SIG
BIT 15
MSB
BIT 14
BIT 5
BIT 4
Hi-Z
24331fa

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  • 英文版
    Differential Input 16-Bit No Latency DS ADC
    LINEAR
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    Linear Integrated Systems [Differential Input 16-Bit No Lat...
    LINEAR

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