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LTC2433-1

APPLICATIO S I FOR ATIO

translates into about 7.15 鈥?10

鈥?

鈥?f

EOSC

LSB additional INL

error. Figure 23 shows the typical INL error due to the

source resistance driving the REF

+

or REF

鈥?/div>

pins when

large C

REF

values are used. The effect of the source

resistance on the two reference pins is additive with

respect to this INL error. In general, matching of source

impedance for the REF

+

and REF

鈥?/div>

pins does not help the

gain or the INL error. The user is thus advised to minimize

the combined source impedance driving the REF

+

and

REF

鈥?/div>

pins rather than to try to match it.

The magnitude of the dynamic reference current depends

upon the size of the very stable internal sampling capaci-

tors and upon the accuracy of the converter sampling

clock. The accuracy of the internal clock over the entire

temperature and power supply range is typical better than

0.5%. Such a specification can also be easily achieved by

an external clock. When relatively stable resistors

(50ppm/掳C) are used for the external source impedance

seen by REF

+

and REF

鈥?/div>

, the expected drift of the dynamic

current gain error will be insignificant (about 1% of its

value over the entire temperature and voltage range). Even

for the most stringent applications a one-time calibration

operation may be sufficient.

1

R

SOURCE

= 1000鈩?/div>

INL (LSB)

0

鈥?

鈥?.5 鈥?.4鈥?.3鈥?.2鈥?.1 0 0.1 0.2 0.3 0.4 0.5

V

INDIF

/V

REFDIF

V

CC

= 5V

F

O

= GND

REF+ = 5V

C

REF

= 10碌F

T

A

= 25掳C

REF鈥?= GND

24331 F23

V

INCM

= 0.5 鈥?(IN

+

+ IN

鈥?/div>

) = 2.5V

Figure 23. INL vs Differential Input Voltage (V

IN

= IN

+

鈥?IN

鈥?/div>

)

and Reference Source Resistance (R

SOURCE

at REF

+

and REF

鈥?/div>

for Large C

REF

Values (C

REF

鈮?/div>

1碌F)

24

U

In addition to the reference sampling charge, the reference

pins ESD protection diodes have a temperature dependent

leakage current. This leakage current, nominally 1nA

(卤10nA max), results in a small gain error. A 100鈩?source

resistance will create a 0.05碌V typical and 0.5碌V maxi-

mum full-scale error.

Output Data Rate

When using its internal oscillator, the LTC2433-1 can

produce up to 6.8 readings per second. The actual output

data rate will depend upon the length of the sleep and data

output phases which are controlled by the user and which

can be made insignificantly short. When operated with an

external conversion clock (F

O

connected to an external

oscillator), the LTC2433-1 output data rate can be in-

creased as desired. The duration of the conversion phase

is 20510/f

EOSC

. If f

EOSC

= 139,800Hz, the converter be-

haves as if the internal oscillator is used with simultaneous

50Hz/60Hz. There is no significant difference in the

LTC2433-1 performance between these two operation

modes.

An increase in f

EOSC

over the nominal 139,800Hz will

translate into a proportional increase in the maximum

output data rate. This substantial advantage is neverthe-

less accompanied by three potential effects, which must

be carefully considered.

First, a change in f

EOSC

will result in a proportional change

in the internal notch position and in a reduction of the

converter differential mode rejection at the power line

frequency. In many applications, the subsequent perfor-

mance degradation can be substantially reduced by rely-

ing upon the LTC2433-1鈥檚 exceptional common mode

rejection and by carefully eliminating common mode to

differential mode conversion sources in the input circuit.

The user should avoid single-ended input filters and

should maintain a very high degree of matching and

symmetry in the circuits driving the IN

+

and IN

鈥?/div>

pins.

Second, the increase in clock frequency will increase

proportionally the amount of sampling charge transferred

through the input and the reference pins. If large external

24331fa

W

U U

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