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CD54HC4059F3A Datasheet

  • CD54HC4059F3A

  • High-Speed CMOS Logic CMOS Programmable Divide-by-N Counter

  • 208.19KB

  • 12页

  • TI

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CD54HC4059, CD74HC4059
The counter should always be put in the master preset mode
before the
梅5
mode is selected. Whenever the master preset
mode is used, control signals K
b
= 鈥渓ow鈥?and K
c
= 鈥渓ow鈥?must
be applied for at least 3 full clock pulses.
After Preset Mode inputs have been changed to one of the
梅
modes, the next positive-going clock transition changes an
internal 铿俰p-铿俹p so that the countdown can begin at the
second positive-going clock transition. Thus, after an MP
(Master Preset) mode, there is always one extra count
before the output goes high. Figure 1 illustrates a total count
of 3 (梅8 mode). If the Master Preset mode is started two
clock cycles or less before an output pulse, the output pulse
will appear at the time due. If the Master Preset Mode is not
used, the counter jumps back to the 鈥淛am鈥?count when the
output pulse appears.
A 鈥渉igh鈥?on the Latch Enable input will cause the counter
output to remain high once an output pulse occurs, and to
remain in the high state until the latch input returns to 鈥渓ow鈥?
If the Latch Enable is 鈥渓ow鈥? the output pulse will remain high
for only one cycle of the clock-input signal.
Pinout
CD54HC4059
(CERDIP)
CD74HC4059
(PDIP, SOIC)
TOP VIEW
CP 1
LE 2
J1 3
J2 4
J3 5
J4 6
J16 7
J15 8
J14 9
J13 10
K
c
11
GND 12
24 V
CC
23 Q
22 J5
21 J6
20 J7
19 J8
18 J9
17 J10
16 J11
15 J12
14 K
a
13 K
b
Functional Diagram
J1 - J16
CP
K
a
K
b
K
c
LE
f IN
-
Q =
铮?/div>
------
铮?/div>
铮?/div>
N
铮?/div>
TRUTH TABLE
COUNTER RANGE
MODE SELECT INPUT
FIRST COUNTING SECTION
CAN BE
PRESET
MODE
TO A MAX
DIVIDES-BY
OF:
2
4
5
(Note 2)
8
10
1
3
4
7
9
Master Preset
(NOTE 1)
JAM
INPUTS
USED:
J1
J1, J2
J1, J2, J3
J1, J2, J3
J1, J2, J3, J4
LAST COUNTING SECTION
CAN BE
PRESET
MODE
TO A MAX
DIVIDES-BY
OF:
8
4
2
2
1
7
3
1
1
0
Master Preset
(NOTE 1)
JAM
INPUTS
USED:
J2, J3, J4
J3, J4
J4
J4
-
DESIGN
EXTENDED
K
a
H
L
H
L
H
X
K
b
H
H
L
L
H
L
K
c
H
H
H
H
L
L
MAX
15,999
15,999
9,999
15,999
9,999
-
MAX
17,331
18,663
13,329
21,327
16,659
-
X = Don鈥檛 care
NOTES:
1. J1 = Least Signi铿乧ant Bit. J4 = Most Signi铿乧ant Bit.
2. Operation in the 5mode (1st counting section) requires going through the Master Preset mode prior to going into the 5mode. At power
turn-on, Kc must be 鈥渓ow鈥?for a period of 3 input clock pulses after VCC reaches a minimum of 3V.
2

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