CD54HC4059, CD74HC4059
Test Circuits and Waveforms
t
r
= 6ns
t
r
C
L
CLOCK
90%
10%
t
f
C
L
t
WL
+ t
WH
=
I
fC
L
V
CC
50%
10%
t
WL
50%
50%
GND
t
WH
INVERTING
OUTPUT
t
THL
t
TLH
90%
50%
10%
t
PHL
t
PLH
INPUT
90%
50%
10%
t
f
= 6ns
V
CC
GND
NOTE: Outputs should be switching from 10% V
CC
to 90% V
CC
in
accordance with device truth table. For f
MAX
, input duty cycle = 50%.
FIGURE 2. HC CLOCK PULSE RISE AND FALL TIMES AND
PULSE WIDTH
FIGURE 3. HC TRANSITION TIMES AND PROPAGATION
DELAY TIMES, COMBINATION LOGIC
t
r
C
L
CLOCK
INPUT
90%
10%
t
H(H)
t
f
C
L
V
CC
50%
GND
t
H(L)
V
CC
DATA
INPUT
t
SU(H)
t
TLH
90%
OUTPUT
t
PLH
t
REM
V
CC
SET, RESET
OR PRESET
t
SU(L)
t
THL
90%
50%
10%
t
PHL
50%
GND
50%
GND
IC
C
L
50pF
FIGURE 4. HC SETUP TIMES, HOLD TIMES, REMOVAL
TIME, AND PROPAGATION DELAY TIMES FOR EDGE
TRIGGERED SEQUENTIAL LOGIC CIRCUITS
6