SC16C654DBIB64 Datasheet

  • SC16C654DBIB64

  • 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.), with 64-byt...

  • 292.47KB

  • 58页

  • PHILIPS

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Philips Semiconductors
SC16C654B/654DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
Table 2:
Symbol
Pin description
鈥ontinued
Pin
PLCC68 LQFP64 HVQFN48 LFBGA6
4
Type Description
RIA
RIB
RIC
RID
RTSA
RTSB
RTSC
RTSD
8
28
42
62
14
22
48
56
63
19
30
50
5
13
36
44
-
-
23
-
3
11
29
-
A2
J3
K8
A9
C2
H2
H9
C10
I
Ring Indicator (active LOW).
These inputs are associated
with individual UART channels, A through D. A logic 0 on this
pin indicates the modem has received a ringing signal from
the telephone line. A logic 1 transition on this input pin will
generate an interrupt.
Request to Send (active LOW).
These outputs are
associated with individual UART channels, A through D. A
logic 0 on the RTS pin indicates the transmitter has data
ready and waiting to send. Writing a logic 1 in the modem
control register MCR[1] will set this pin to a logic 0,
indicating data is available. After a reset this pin will be set to
a logic 1. This pin only affects the transmit and receive
operations when Auto RTS function is enabled via the
Enhanced Feature Register (EFR[6]) for hardware 铿俹w
control operation.
Read/Write strobe.
This function is associated with the
68 mode only. This pin provides the combined functions for
Read or Write strobes.
Logic 1 = Read from UART register selected by CS and
A[0:4].
Logic 0 = Write to UART register selected by CS and A[0:4].
O
R/W
18
-
7
-
I
RXA
RXB
RXC
RXD
7
29
41
63
62
20
29
51
48
13
22
38
A3
K3
J8
B8
I
Receive data input RXA-RXD.
These inputs are associated
with individual serial channel data to the
SC16C654B/654DB. The RX signal will be a logic 1 during
reset, idle (no data), or when the transmitter is disabled.
During the local loop-back mode, the RX input pin is
disabled and TX data is connected to the UART RX input
internally.
Receive Ready (active LOW).
This function is associated
with 68-pin package only. RXRDY contains the wire-ORed
status of all four receive channel FIFOs, RXRDYA-RXRDYD.
A logic 0 indicates receive data ready status, that is, the
RHR is full, or the FIFO has one or more RX characters
available for unloading. This pin goes to a logic 1 when the
FIFO/RHR is empty, or when there are no more characters
available in either the FIFO or RHR. Individual channel RX
status is read by examining individual internal registers via
CS and A[0:4] pin functions.
Transmit data A, B, C, D.
These outputs are associated
with individual serial transmit channel data from the
SC16C654B/654DB. The TX signal will be a logic 1 during
reset, idle (no data), or when the transmitter is disabled.
During the local loop-back mode, the TX output pin is
disabled and TX data is internally connected to the UART
RX input.
RXRDY
38
-
-
-
O
TXA
TXB
TXC
TXD
17
19
51
53
8
10
39
41
6
8
32
34
E2
F2
F10
E10
O
9397 750 14965
漏 Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 鈥?20 June 2005
13 of 58

SC16C654DBIB64 产品属性

  • NXP

  • UART 接口集成电路

  • 4

  • 5 Mbps

  • 5.5 V

  • 2.25 V

  • 6 mA

  • + 85 C

  • - 40 C

  • LQFP-64

  • Bulk

  • SMD/SMT

  • 2.5 V, 3.3 V, 5 V

  • 800

  • IrDA

  • SC16C654DBIB64,157

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