Philips Semiconductors
SC16C654B/654DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
time. In addition, the four selectable levels of FIFO trigger interrupt and automatic
hardware/software 铿俹w control is uniquely provided for maximum data throughput
performance, especially when operating in a multi-channel environment. The combination
of the above greatly reduces the bandwidth requirement of the external controlling CPU,
increases performance, and reduces power consumption.
The SC16C654B/654DB combines the package interface modes of the 16C454/554 and
68C454/554 series on a single integrated chip. The 16 mode interface is designed to
operate with the Intel-type of microprocessor bus, while the 68 mode is intended to
operate with Motorola and other popular microprocessors. Following a reset, the
SC16C654B/654DB is downward compatible with the 16C454/554 or the 68C454/554,
dependent on the state of the interface mode selection pin, 16/68.
The SC16C654B/654DB is capable of operation to 1.5 Mbit/s with a 24 MHz crystal and
up to 5 Mbit/s with an external clock input (at 3.3 V and 5 V; at 2.5 V the max speed is
3 Mbit/s). With a crystal of 14.7464 MHz, and through a software option, the user can
select data rates up to 460.8 kbit/s or 921.6 kbit/s, 8 times faster than the 16C554.
The rich feature set of the SC16C654B/654DB is available through internal registers.
Automatic hardware/software 铿俹w control, selectable transmit and receive FIFO trigger
levels, selectable TX and RX baud rates, infrared encoder/decoder interface, modem
interface controls, and a sleep mode are all standard features. MCR[5] provides a facility
for turning off (Xon) software 铿俹w control with any incoming (RX) character. In the
16 mode, INTSEL and MCR[3] can be con铿乬ured to provide a software controlled or
continuous interrupt capability. Due to pin limitations of the 64-pin package, this feature is
offered by two different LQFP64 packages. The SC16C654DB operates in the continuous
interrupt enable mode by bonding INTSEL to V
CC
internally. The SC16C654B operates in
conjunction with MCR[3] by bonding INTSEL to GND internally.
The PLCC68 SC16C654B package offers a clock select pin to allow system/board
designers to preset the default baud rate table. The CLKSEL pin selects the 1脳 or 4脳
pre-scalable baud rate generator table during initialization, but can be overridden following
initialization by MCR[7].
9397 750 14965
漏 Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 鈥?20 June 2005
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