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SC16C654DBIB64 Datasheet

  • SC16C654DBIB64

  • 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.), with 64-byt...

  • 292.47KB

  • 58页

  • PHILIPS

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Philips Semiconductors
SC16C654B/654DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
6.2 Internal registers
The SC16C654B/654DB provides 17 internal registers for monitoring and control. These
registers are shown in
Table 5.
Twelve registers are similar to those already available in
the standard 16C554. These registers function as data holding registers (THR/RHR),
interrupt status and control registers (IER/ISR), a FIFO control register (FCR), line status
and control registers (LCR/LSR), modem status and control registers (MCR/MSR),
programmable data rate (clock) control registers (DLL/DLM), and a user accessible
scratchpad register (SPR). Beyond the general 16C554 features and capabilities, the
SC16C654B/654DB offers an enhanced feature register set (EFR, Xon/Xoff1-2) that
provides on-board hardware/software 铿俹w control. Register functions are more fully
described in the following paragraphs.
Table 5:
A2
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
[1]
[2]
[3]
Internal registers decoding
A1
0
0
1
1
0
0
1
1
0
0
1
0
0
1
1
A0
0
1
0
1
0
1
0
1
0
1
0
0
1
0
1
Read mode
Receive Holding Register
Interrupt Enable Register
Interrupt Status Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
Scratchpad Register
LSB of Divisor Latch
MSB of Divisor Latch
Enhanced Feature Register
Xon1 word
Xon2 word
Xoff1 word
Xoff2 word
Write mode
Transmit Holding Register
Interrupt Enable Register
FIFO Control Register
Line Control Register
Modem Control Register
n/a
n/a
Scratchpad Register
LSB of Divisor Latch
MSB of Divisor Latch
Enhanced Feature Register
Xon1 word
Xon2 word
Xoff1 word
Xoff2 word
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LSR, SPR)
[1]
Baud rate register set (DLL/DLM)
[2]
Enhanced register set (EFR, Xon/off 1-2)
[3]
These registers are accessible only when LCR[7] is a logic 0.
These registers are accessible only when LCR[7] is a logic 1.
Enhanced Feature Register, Xon1, 2 and Xoff1, 2 are accessible only when the LCR is set to 鈥楤Fh鈥?
6.3 FIFO operation
The 64-byte transmit and receive data FIFOs are enabled by the FIFO Control Register
(FCR) bit 0. With SC16C554 devices, the user can set the receive trigger level, but not the
transmit trigger level. The SC16C654B/654DB provides independent trigger levels for both
receiver and transmitter. To remain compatible with SC16C554, the transmit interrupt
trigger level is set to 8 following a reset. It should be noted that the user can set the
transmit trigger levels by writing to the FCR register, but activation will not take place until
EFR[4] is set to a logic 1. The receiver FIFO section includes a time-out function to ensure
data is delivered to the external CPU. An interrupt is generated whenever the Receive
9397 750 14965
漏 Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 鈥?20 June 2005
17 of 58

SC16C654DBIB64 产品属性

  • NXP

  • UART 接口集成电路

  • 4

  • 5 Mbps

  • 5.5 V

  • 2.25 V

  • 6 mA

  • + 85 C

  • - 40 C

  • LQFP-64

  • Bulk

  • SMD/SMT

  • 2.5 V, 3.3 V, 5 V

  • 800

  • IrDA

  • SC16C654DBIB64,157

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