Philips Semiconductors
SC16C654B/654DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
SC16C654B/654DB
TRANSMIT
FIFO
REGISTERS
DATA BUS
AND
CONTROL
LOGIC
FLOW
CONTROL
LOGIC
IR
ENCODER
TRANSMIT
SHIFT
REGISTER
TXA to TXD
D0 to D7
IOR
IOW
RESET
INTERCONNECT BUS LINES
AND
CONTROL SIGNALS
RECEIVE
FIFO
REGISTERS
RECEIVE
SHIFT
REGISTER
MCR[4] = 1
RXA to RXD
A0 to A2
CSA to CSD
REGISTER
SELECT
LOGIC
FLOW
CONTROL
LOGIC
IR
DECODER
RTSA to RTSD
CTSA to CTSD
DTRA to DTRD
MODEM
CONTROL
LOGIC
INTA to INTD
TXRDY
RXRDY
INTERRUPT
CONTROL
LOGIC
CLOCK AND
BAUD RATE
GENERATOR
DSRA to DSRD
OP1A to OP1D
RIA to RID
OP2A to OP2D
CDA to CDD
002aaa876
XTAL1 XTAL2
Fig 12. Internal loop-back mode diagram
9397 750 14965
漏 Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 鈥?20 June 2005
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