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SC16C654DBIB64 Datasheet

  • SC16C654DBIB64

  • 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.), with 64-byt...

  • 292.47KB

  • 58页

  • PHILIPS

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Philips Semiconductors
SC16C654B/654DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
7. Register descriptions
Table 8
details the assigned bit functions for the SC16C654B/654DB internal registers.
The assigned bit functions are more fully de铿乶ed in
Section 7.1
through
Section 7.11.
Table 8:
SC16C654B/654DB internal registers
Bit 6
bit 6
bit 6
Bit 5
bit 5
bit 5
Bit 4
bit 4
bit 4
Sleep
mode
[3]
Bit 3
bit 3
bit 3
modem
status
interrupt
Bit 2
bit 2
bit 2
Bit 1
bit 1
bit 1
Bit 0
bit 0
bit 0
receive
holding
register
FIFO
enable
INT
status
word
length
bit 0
DTR
receive
data
ready
鈭咰TS
bit 0
bit 0
bit 8
Cont-0
Tx, Rx
Control
A2 A1 A0 Register Default
[1]
Bit 7
General Register Set
[2]
0
0
0
0
0
0
0
0
1
RHR
THR
IER
XX
XX
00
bit 7
bit 7
RTS
Xoff
CTS
interrupt interrupt interrupt
[3]
[3]
[3]
receive
transmit
line status holding
interrupt
register
XMIT
RCVR
FIFO reset FIFO
reset
INT
priority
bit 1
stop bits
INT
priority
bit 0
word
length
bit 1
RTS
overrun
error
鈭咲SR
bit 1
bit 1
bit 9
0
1
0
FCR
00
RCVR
trigger
(MSB)
FIFOs
enabled
divisor
latch
enable
Clock
select
[3]
FIFO
data
error
CD
bit 7
bit 7
bit 15
Auto
CTS
RCVR
trigger
(LSB)
FIFOs
enabled
set
break
TX
TX trigger DMA
trigger
(LSB)
[3]
mode
(MSB)
[3]
select
[4]
INT
priority
bit 4
INT
priority
bit 3
INT
priority
bit 2
parity
enable
0
1
0
ISR
01
0
1
1
LCR
00
set parity even
parity
1
1
0
0
0
1
MCR
LSR
00
60
IR
Xon
[3]
Any
[3]
enable
trans.
empty
RI
bit 6
bit 6
bit 14
Auto
RTS
trans.
holding
empty
DSR
bit 5
bit 5
bit 13
Special
char.
select
loop back OP2, INTx OP1
enable
break
interrupt
CTS
bit 4
bit 4
bit 12
framing
error
鈭咰D
bit 3
bit 3
bit 11
parity
error
鈭哛I
bit 2
bit 2
bit 10
1
1
0
0
0
1
1
0
0
1
0
1
0
1
0
MSR
SPR
DLL
DLM
EFR
X0
FF
XX
XX
00
Special Register Set
[5]
Enhanced Register Set
[6]
Cont-3 Tx, Cont-2 Tx, Cont-1
Enable
IER[4:7], Rx Control Rx Control Tx, Rx
Control
ISR[4:5],
FCR[4:5],
MCR[5:7]
bit 4
bit 12
bit 4
bit 12
bit 3
bit 11
bit 3
bit 11
bit 2
bit 10
bit 2
bit 10
bit 1
bit 9
bit 1
bit 9
1
1
1
1
[1]
[2]
[3]
[4]
[5]
[6]
0
0
1
1
0
1
0
1
Xon-1
Xon-2
Xoff-1
Xoff-2
00
00
00
00
bit 7
bit 15
bit 7
bit 15
bit 6
bit 14
bit 6
bit 14
bit 5
bit 13
bit 5
bit 13
bit 0
bit 8
bit 0
bit 8
The value shown represents the register鈥檚 initialized HEX value; X = not applicable.
These registers are accessible only when LCR[7] = 0.
These bits are only accessible when EFR[4] is set.
This function is not supported in the HVQFN48 package; TXRDY and RXRDY are removed.
The Special Register set is accessible only when LCR[7] is set to a logic 1.
Enhanced Feature Register, Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to 鈥楤Fh鈥?
漏 Koninklijke Philips Electronics N.V. 2005. All rights reserved.
9397 750 14965
Product data sheet
Rev. 02 鈥?20 June 2005
24 of 58

SC16C654DBIB64 产品属性

  • NXP

  • UART 接口集成电路

  • 4

  • 5 Mbps

  • 5.5 V

  • 2.25 V

  • 6 mA

  • + 85 C

  • - 40 C

  • LQFP-64

  • Bulk

  • SMD/SMT

  • 2.5 V, 3.3 V, 5 V

  • 800

  • IrDA

  • SC16C654DBIB64,157

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