Philips Semiconductors
SC16C654B/654DB
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
4. Block diagram
SC16C654B/654DB
TRANSMIT
FIFO
REGISTERS
TRANSMIT
SHIFT
REGISTER
TXA to TXD
D0 to D7
IOR
IOW
RESET
DATA BUS
AND
CONTROL
LOGIC
FLOW
CONTROL
LOGIC
IR
ENCODER
INTERCONNECT BUS LINES
AND
CONTROL SIGNALS
RECEIVE
FIFO
REGISTERS
RECEIVE
SHIFT
REGISTER
RXA to RXD
A0 to A2
CSA to CSD
REGISTER
SELECT
LOGIC
FLOW
CONTROL
LOGIC
IR
DECODER
16/68
DTRA to DTRD
RTSA to RTSD
INTA to INTD
TXRDY
RXRDY
INTERRUPT
CONTROL
LOGIC
CLOCK AND
BAUD RATE
GENERATOR
MODEM
CONTROL
LOGIC
CTSA to CTSD
RIA to RID
CDA to CDD
DSRA to DSRD
INTSEL
002aaa871
XTAL1 XTAL2
CLKSEL
Fig 1. Block diagram of SC16C654B/654DB (16 mode)
9397 750 14965
漏 Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 鈥?20 June 2005
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