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A82DL3244UG-70U Datasheet

  • A82DL3244UG-70U

  • Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82D...

  • 932.05KB

  • 60页

  • AMICC

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A82DL32x4T(U) Series
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device energy
consumption. The device automatically enables this mode
when addresses remain stable for t
ACC
+30ns. The automatic
sleep mode is independent of the
CE_F
,
WE
and
OE
control signals. Standard address access timings provide
new data when addresses are changed. While in sleep
mode, output data is latched and always available to the
system. I
CC4_F
in the DC Characteristics table represents the
automatic sleep mode current specification.
The
RESET
pin may be tied to the system reset circuitry. A
system reset would thus also reset the Flash memory,
enabling the system to read the boot-up firmware from the
Flash memory.
If
RESET
is asserted during a program or erase operation,
the RY/
BY
pin remains a 鈥?鈥?(busy) until the internal reset
operation is complete, which requires a time t
READY
(during
Embedded Algorithms). The system can thus monitor
RY/
BY
to determine whether the reset operation is
complete. If
RESET
is asserted when a program or erase
operation is not executing (RY/
BY
pin is 鈥?鈥?, the reset
operation is completed within a time of t
READY
(not during
Embedded Algorithms). The system can read data t
RH
after
the
RESET
pin return to V
IH
.
Refer to the AC Characteristics tables for
RESET
parameters and diagram.
RESET
: Hardware Reset Pin
The
RESET
pin provides a hardware method of resetting
the device to reading array data. When the system drives the
RESET
pin low for at least a period of t
RP
, the device
immediately terminates any operation in progress, tristates
all data output pins, and ignores all read/write attempts for
the duration of the
RESET
pulse. The device also resets the
internal state machine to reading array data. The operation
that was interrupted should be reinitiated once the device is
ready to accept another command sequence, to ensure data
integrity.
Current is reduced for the duration of the
RESET
pulse.
When
RESET
is held at VSS
卤
0.3V, the device draws
CMOS standby current (I
CC4_F
). If
RESET
is held at V
IL
but
not within VSS
卤
0.3V, the standby current will be greater.
Output Disable Mode
When the
OE
input is at V
IH
, output from the device is
disabled. The output pins are placed in the high impedance
state.
Table 2. A82DL32x4T(U) Device Bank Divisions
Device
Part Number
A82DL3224
A82DL3234
A82DL3244
Bank 1
Megabits
4 Mbit
8 Mbit
16 Mbit
Sector Sizes
Eight 8 Kbyte/4 Kword,
three 64 Kbyte/32 Kword
Eight 8 Kbyte/4 Kword,
seven 64 Kbyte/32 Kword
Eight 8 Kbyte/4 Kword,
fifteen 64 Kbyte/32 Kword
Megabits
28 Mbit
24 Mbit
16 Mbit
Bank 2
Sector Sizes
Fifty-six
64 Kbyte/32 Kword
Forty-eight
64 Kbyte/32 Kword
Thirty-two
64 Kbyte/32 Kword
PRELIMINARY
(August, 2005, Version 0.0)
11
AMIC Technology, Corp.

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