A82DL3244UG-70U Datasheet

  • A82DL3244UG-70U

  • Stacked Multi-Chip Package (MCP) Flash Memory and SRAM, A82D...

  • 932.05KB

  • 60页

  • AMICC

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A82DL32x4T(U) Series
AC CHARACTERISTICS
Figure 20. Toggle Bit Timings (During Embedded Algorithms)
t
AHT
Addresses
t
AHT
t
ASO
t
AS
CE_F
t
OEH
t
CEPH
WE
OE
t
OEPH
t
DH
I/O
6
,
I/O
2
Valid Status
Valid Status
(first read)
t
OE
~
~
~
~
Valid Status
(second read)
Valid Status
~
~
~
~
~
~
Valid Data
(stop togging)
RY/BY
Note: VA = Valid Address; not required for I/O
6
. Illustration shows first two status cycle after command sequence, last status
read cycle, and array data read cycle.
Figure 21. I/O
2
vs. I/O
6
Enter
Embedded
Erasing
WE
Erase
Suspend
Enter Erase
Suspend Program
Erase
Resume
~
~
~
~
~
~
~
~
~
~
Erase
Erase Suspend
Read
Erase
Suspend
Program
Erase Suspend
Read
Erase
~
~
Erase
Complete
~
~
~
~
~
~
~
~
~
~
~
~
I/O
6
~
~
~
~
I/O
2
I/O
2
and I/O
6
toggle with OE and CE_F
Note : Both I/O
6
and I/O
2
toggle with OE or CE_F. See the text on I/O
6
and I/O
2
in the section "Write Operation Status" for
more information.
PRELIMINARY
(August, 2005, Version 0.0)
44
AMIC Technology, Corp.
~
~
~
~

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