A82DL32x4T(U) Series
Timing Waveforms (continued)
Read Cycle 4
(1)
t
RC
Address
t
AA
OE
t
OE
t
OH
t
OLZ
5
CE1_S
t
ACE1
t
CLZ1
5
t
CHZ1
5
CE2_S
t
ACE2
t
CLZ2
5
t
OHZ
5
t
CHZ2
5
DOUT
Notes: 1. WE is high for Read Cycle.
2. Device is continuously enabled
CE1_S
= V
IL
and
CE2_S
= V
IH
.
3. Address valid prior to or coincident with
CE1_S
transition low.
4. OE = V
IL
.
5. Transition is measured
卤
500mV from steady state. This parameter is sampled and not 100% tested.
6.
CE2_S
is high.
7.
CE1_S
is low.
8. Address valid prior to or coincident with
CE2_S
transition high.
Write Cycle 1
(6)
(Write Enable Controlled)
t
WC
Address
t
AW
t
CW
5
t
WR
3
CE1_S
(4)
CE2_S
t
AS
1
(4)
t
WP
2
WE
t
D
W
t
DH
DIN
t
WHZ
t
O
W
DOUT
PRELIMINARY
(August, 2005, Version 0.0)
53
AMIC Technology, Corp.