E28F640J3C-150 Datasheet

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256-Mbit J3 (x8/x16)

Figure 25. Clear Lock-Bit Flowchart

Start

Bus

Operation

Write

Command

Clear Block

Lock-Bits Setup

Clear Block or

Lock-Bits Confirm

Comments

Data = 60H

Addr = X

Data = D0H

Addr = X

Status Register Data

Check SR.7

1 = WSM Ready

0 = WSM Busy

Write 60H

Write

Write D0H

Read

Read Status Register

Standby

SR.7 =

1

Full Status

Check if Desired

Clear Block Lock-Bits

Complete

0

Write FFH after the clear lock-bits operation to place device in read

array mode.

FULL STATUS CHECK PROCEDURE

Read Status Register

Data (See Above)

1

SR.3 =

0

1

SR.4,5 =

0

1

SR.5 =

0

Clear Block Lock-Bits

Successful

Clear Block Lock-Bits

Error

Command Sequence

Error

Voltage Range Error

Standby

Bus

Operation

Standby

Command

Comments

Check SR.3

1 = Programming Voltage Error

Detect

Check SR.4, 5

Both 1 = Command Sequence

Error

Check SR.5

1 = Clear Block Lock-Bits Error

Standby

SR.5, SR.4, and SR.3 are only cleared by the Clear Status Register

command.

If an error is detected, clear the status register before attempting retry

or other error recovery.

66

Datasheet

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