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24LC08BT-I/SNG Datasheet

  • 24LC08BT-I/SNG

  • 8K IC SERIAL EEPROM

  • 368.84KB

  • 26页

  • MICROCHIP   MICROCHIP

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24AA08/24LC08B
7.0
READ OPERATION
7.3
Sequential Read
Read operations are initiated in the same way as write
operations, with the exception that the R/W bit of the
slave address is set to 鈥?/div>
1
鈥? There are three basic types
of read operations: current address read, random read
and sequential read.
Sequential reads are initiated in the same way as a
random read, except that once the 24XX08 transmits
the first data byte, the master issues an acknowledge
as opposed to a Stop condition in a random read. This
directs the 24XX08 to transmit the next sequentially-
addressed 8-bit word (Figure 6-3).
To provide sequential reads, the 24XX08 contains an
internal address pointer that is incremented by one
upon completion of each operation. This address
pointer allows the entire memory contents to be serially
read during one operation.
7.1
Current Address Read
The 24XX08 contains an address counter that main-
tains the address of the last word accessed, internally
incremented by 鈥?/div>
1
鈥? Therefore, if the previous access
(either a read or write operation) was to address
n
, the
next current address read operation would access data
from address
n + 1
. Upon receipt of the slave address
with R/W bit set to 鈥?/div>
1
鈥? the 24XX08 issues an acknowl-
edge and transmits the 8-bit data word. The master will
not acknowledge the transfer but does generate a Stop
condition and the 24XX08 discontinues transmission
(Figure 6-1).
7.4
Noise Protection
The 24XX08 employs a V
CC
threshold detector circuit
which disables the internal erase/write logic if the V
CC
is below 1.5V at nominal conditions.
The SCL and SDA inputs have Schmitt Trigger and
filter circuits which suppress noise spikes to assure
proper device operation, even on a noisy bus.
7.2
Random Read
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, the word address must first
be set. This is accomplished by sending the word
address to the 24XX08 as part of a write operation.
Once the word address is sent, the master generates a
Start condition following the acknowledge. This
terminates the write operation, but not before the
internal address pointer is set. The master then issues
the control byte again, but with the R/W bit set to a 鈥?/div>
1
鈥?
The 24XX08 will then issue an acknowledge and trans-
mit the 8-bit data word. The master will not acknowl-
edge the transfer but does generate a Stop condition
and the 24XX08 will discontinue transmission
(Figure 6-2).
FIGURE 7-1:
CURRENT ADDRESS READ
BUS ACTIVITY
MASTER
S
T
A
R
T
S
A
C
K
N
O
A
C
K
Control
Byte
S
T
O
P
P
Data (n)
SDA LINE
BUS ACTIVITY
漏
2005 Microchip Technology Inc.
DS21710D-page 9

24LC08BT-I/SNG 产品属性

  • Microchip

  • 电可擦除可编程只读存储器

  • 8 Kbit

  • 4 Block x 256 x 8

  • 200 yr

  • 0.4 MHz

  • 3 mA

  • 2.5 V, 5.5 V

  • + 85 C

  • SMD/SMT

  • SOIC-8

  • 900 ns

  • I2C

  • - 40 C

  • Reel

  • 5.5 V

  • 2.5 V

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