CD74HCT40105MTE4 Datasheet

  • CD74HCT40105MTE4

  • High-Speed CMOS Logic 4-Bit x 16-Word FIFO Register

  • 317.75KB

  • 19页

  • TI

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CD54HC40105, CD74HC40105, CD54HCT40105, CD74HCT40105
MASTER
RESET
SHIFT IN
(DATA VALID)
INPUTS
鈮?/div>
180ns
(NOTE 6)
SHIFT OUT
SHIFT-OUT PULSES
HAVE NO EFFECT
INPUT READY
(CLEAR OUT)
(NOTE 5)
OUTPUT READY
(DATA VALID)
DATA IN
(Db)
THREE-STATE
(OUTPUT
ENABLE)
DATA OUT
(NOTE 5)
SHIFT-IN PULSES
HAVE NO EFFECT
鈮?/div>
180ns
(NOTE 7)
OUTPUTS
INPUTS
1 0
1 1
1 0 0 1 1 0
10 1 0 1 0
HIGH Z
1
0 1 1
1
0
INVALID
(UNKNOWN)
NOTES:
5. Data valid goes to high level in advance of the data out by a maximum of 38ns at V
CC
= 4.5V for C
L
= 50pF and T
A
= 25
o
C.
6. At V
CC
= 4.5V, ripple time from position 1 to position 16.
7. At V
CC
= 4.5V, ripple time from position 16 to position 1.
FIGURE 13. TIMING DIAGRAM FOR THE CD74HC/HCT40105
13

CD74HCT40105MTE4 产品属性

  • 250

  • 集成电路 (IC)

  • 逻辑 - FIFO

  • 74HCT

  • 异步

  • 64 (16 x 4)

  • -

  • -

  • 4.5 V ~ 5.5 V

  • -55°C ~ 125°C

  • 表面贴装

  • 16-SOIC(0.154",3.90mm 宽)

  • 16-SOIC N

  • 带卷 (TR)

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