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SC16C754BIB80 Datasheet

  • SC16C754BIB80

  • 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte...

  • 249.81KB

  • 50页

  • PHILIPS

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Philips Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
Table 10
lists and describes the SC16C754B internal registers.
Table 10:
SC16C754B internal registers
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Read/
Write
R
W
A2 A1 A0 Register Bit 7
General Register set
[1]
0
0
0
0
0
0
0
0
1
RHR
THR
IER
bit 7
bit 7
0/CTS
interrupt
enable
[2]
RX
trigger
level
(MSB)
FCR[0]
bit 6
bit 6
0/RTS
interrupt
enable
[2]
bit 5
bit 5
0/Xoff
[2]
bit 4
bit 4
bit 3
bit 3
bit 2
bit 2
bit 1
bit 1
THR
empty
interrupt
bit 0
bit 0
0/X Sleep modem receive
mode
[2]
status
line status
interrupt interrupt
0/TX
trigger
level
(LSB)
[2]
0/Xoff
DMA
mode
select
TX FIFO
reset
Rx data R/W
available
interrupt
W
0
1
0
FCR
RX trigger 0/TX
level (LSB) trigger
level
(MSB)
[2]
FCR[0]
0/CTS,
RTS
RX FIFO FIFO
reset
enable
0
1
0
IIR
interrupt interrupt
priority
priority
bit 2
bit 1
number of
stop bits
FIFO
ready
enable
interrupt
priority
bit 0
word
length
bit 1
RTS
interrupt R
status
word
length
bit 0
DTR
R/W
0
1
1
LCR
DLAB
break
control bit
TCR and
TLR
enable
[2]
set parity parity type parity
select
enable
0/Xon
Any
[2]
0/enable IRQ
loop-back enable
OP
break
interrupt
CTS
bit 4
bit 4
bit 4
RX FIFO
A status
bit 4
bit 12
framing
error
鈭咰D
bit 3
bit 3
bit 3
1
0
0
MCR
1脳 or
1脳/4
clock
[2]
0/error in
RX FIFO
CD
bit 7
bit 7
bit 7
RX FIFO
D status
bit 7
bit 15
R/W
1
1
1
1
1
1
0
1
1
1
1
1
1
0
1
0
1
1
LSR
MSR
SPR
TCR
TLR
FIFO
Rdy
DLL
DLH
EFR
THR and
THR
TSR empty empty
RI
bit 6
bit 6
bit 6
RX FIFO
C status
bit 6
bit 14
DSR
bit 5
bit 5
bit 5
RX FIFO
B status
bit 5
bit 13
parity error overrun
error
鈭哛I
bit 2
bit 2
bit 2
鈭咲SR
bit 1
bit 1
bit 1
data in
receiver
鈭咰TS
bit 0
bit 0
bit 0
R
R
R/W
R/W
R/W
TX FIFO TX FIFO
D status C status
bit 3
bit 11
bit 2
bit 10
TX FIFO TX FIFO R
B status A status
bit 1
bit 9
software
铿俹w
control
bit 1
bit 1
bit 1
bit 1
bit 1
bit 0
bit 8
R/W
R/W
Special Register set
[3]
0
0
0
0
0
1
0
1
0
Enhanced Register set
[4]
Auto CTS Auto RTS
Special
Enable
software software
铿俹w
character enhanced 铿俹w
control
detect
functions control
[2]
bit 2
bit 3
bit 5
bit 5
bit 5
bit 5
bit 4
bit 4
bit 4
bit 4
bit 3
bit 3
bit 3
bit 3
bit 2
bit 2
bit 2
bit 2
software R/W
铿俹w
control
bit 0
bit 0
bit 0
bit 0
bit 0
R/W
R/W
R/W
R/W
1
1
1
1
[1]
[2]
[3]
[4]
0
0
1
1
0
1
0
1
Xon1
Xon2
Xoff1
Xoff2
bit 7
bit 7
bit 7
bit 7
bit 6
bit 6
bit 6
bit 6
These registers are accessible only when LCR[7] = 0.
This bit can only be modi铿乪d if register bit EFR[4] is enabled, that is, if enhanced functions are enabled.
The Special Register set is accessible only when LCR[7] is set to a logic 1.
Enhanced Feature Register; Xon1/Xon2 and Xoff1/Xoff2 are accessible only when LCR is set to 鈥楤Fh鈥?
漏 Koninklijke Philips Electronics N.V. 2005. All rights reserved.
9397 750 14668
Product data sheet
Rev. 02 鈥?13 June 2005
22 of 50

SC16C754BIB80 产品属性

  • 4

  • 5Mbps

  • DMA 信号传输能力、软件可选择传输速率发生器

  • 2.25V 到 5.5V

  • -40°C 到 +85°C

  • LQFP

  • 80

  • No SVHC (18-Jun-2012)

  • 异步

  • 16

  • LQFP

  • -40°C

  • 85°C

  • 5Mbps

  • 80MHz

  • 5Mbps

  • 5V

  • 5V

  • 2.5V

  • 16C754

  • 表??安装

  • 16C754

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