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SC16C754BIB80 Datasheet

  • SC16C754BIB80

  • 5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte...

  • 249.81KB

  • 50页

  • PHILIPS

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Philips Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
7.5 Line Status Register (LSR)
Table 13
shows the line status register bit settings.
Table 13:
Bit
7
Line Status Register bits description
Description
FIFO data error.
logic 0 = no error (normal default condition)
logic 1 = at least one parity error, framing error, or break indication is in the
receiver FIFO. This bit is cleared when no more errors are present in the
FIFO.
6
LSR[6]
THR and TSR empty. This bit is the Transmit Empty indicator.
logic 0 = transmitter hold
and
shift registers are not empty
logic 1 = transmitter hold
and
shift registers are empty
5
LSR[5]
THR empty. This bit is the Transmit Holding Register Empty indicator.
logic 0 = Transmit Hold Register is
not
empty
logic 1 = Transmit Hold Register is empty. The processor can now load up
to 64 bytes of data into the THR if the TX FIFO is enabled.
4
LSR[4]
Break interrupt.
logic 0 = no break condition (normal default condition)
logic 1 = a break condition occurred and associated byte is 00, that is,
RX was LOW for one character time frame
3
LSR[3]
Framing error.
logic 0 = no framing error in data being read from RX FIFO (normal default
condition)
logic 1 = framing error occurred in data being read from RX FIFO, that is,
received data did not have a valid stop bit
2
LSR[2]
Parity error.
logic 0 = no parity error (normal default condition)
logic 1 = parity error in data being read from RX FIFO
1
LSR[1]
Overrun error.
logic 0 = no overrun error (normal default condition)
logic 1 = overrun error has occurred
0
LSR[0]
Data in receiver.
logic 0 = no data in receive FIFO (normal default condition)
logic 1 = at least one character in the RX FIFO
Symbol
LSR[7]
When the LSR is read, LSR[4:2] re铿俥ct the error bits (BI, FE, PE) of the character at the
top of the RX FIFO (next character to be read). The LSR[4:2] registers do not physically
exist, as the data read from the RX FIFO is output directly onto the output data bus,
DI[4:2], when the LSR is read. Therefore, errors in a character are identi铿乪d by reading
the LSR and then reading the RHR.
LSR[7] is set when there is an error anywhere in the RX FIFO, and is cleared only when
there are no more errors remaining in the FIFO.
Reading the LSR does not cause an increment of the RX FIFO read pointer. The RX FIFO
read pointer is incremented by reading the RHR.
9397 750 14668
漏 Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 鈥?13 June 2005
26 of 50

SC16C754BIB80 产品属性

  • 4

  • 5Mbps

  • DMA 信号传输能力、软件可选择传输速率发生器

  • 2.25V 到 5.5V

  • -40°C 到 +85°C

  • LQFP

  • 80

  • No SVHC (18-Jun-2012)

  • 异步

  • 16

  • LQFP

  • -40°C

  • 85°C

  • 5Mbps

  • 80MHz

  • 5Mbps

  • 5V

  • 5V

  • 2.5V

  • 16C754

  • 表??安装

  • 16C754

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