Philips Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
The FIFO Rdy register is a read-only register that can be accessed when any of the two
UARTs is selected CSA - CSD = 0, MCR[2] (FIFO Rdy Enable) is a logic 1, and loop-back
is disabled. The address is 111.
8. Programmer鈥檚 guide
The base set of registers that is used during high-speed data transfer have a
straightforward access method. The extended function registers require special access
bits to be decoded along with the address lines. The following guide will help with
programming these registers. Note that the descriptions below are for individual register
access. Some streamlining through interleaving can be obtained when programming all
the registers.
Table 23:
Command
set baud rate to VALUE1, VALUE2
Register programming guide
Actions
read LCR (03), save in temp
set LCR (03) to 80
set DLL (00) to VALUE1
set DLM (01) to VALUE2
set LCR (03) to temp
set Xoff1, Xon1 to VALUE1, VALUE2
read LCR (03), save in temp
set LCR (03) to BF
set Xoff1 (06) to VALUE1
set Xon1 (04) to VALUE2
set LCR (03) to temp
set Xoff2, Xon2 to VALUE1, VALUE2
read LCR (03), save in temp
set LCR (03) to BF
set Xoff-2 (07) to VALUE1
set Xon-2 (05) to VALUE2
set LCR (03) to temp
set software 铿俹w control mode to VALUE
read LCR (03), save in temp
set LCR (03) to BF
set EFR (02) to VALUE
set LCR (03) to temp
set 铿俹w control threshold to VALUE
read LCR (03), save in temp1
set LCR (03) to BF
read EFR (02), save in temp2
set EFR (02) to 10 + temp2
set LCR (03) to 00
read MCR (04), save in temp3
set MCR (04) to 40 + temp3
set TCR (06) to VALUE
set MCR (04) to temp3
set LCR (03) to BF
set EFR (02) to temp2
set LCR (03) to temp1
9397 750 14668
漏 Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 鈥?13 June 2005
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