Philips Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
[2]
[3]
Maximum frequency =
-------
1
t
3w
RCLK is an internal signal derived from divisor latch LSB (DLL) and divisor latch MSB (DLM) divisor latches.
11.1 Timing diagrams
t
6h
valid
address
t
6s
t
13h
A0 to A2
CSx
t
13d
active
t
15d
t
13w
active
t
16s
t
16h
IOW
D0 to D7
data
002aaa109
Fig 15. General write timing
t
6h
valid
address
t
6s
t
7h
A0 to A2
CSx
t
7d
active
t
9d
t
7w
active
t
12d
t
12h
IOR
D0 to D7
data
002aaa110
Fig 16. General read timing
9397 750 14668
漏 Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 鈥?13 June 2005
38 of 50