SN65LV1023A/SN65LV1224A
10-MHz TO 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SLLS570A 鈥?JUNE 2003 鈥?REVISED JUNE 2003
deserializer switching characteristics over recommended operating supply and temperature
ranges (unless otherwise specified) (continued)
PARAMETER
tRNM
Deserializer noise
margin
TEST CONDITIONS
See Figure 18 and
Note 8
PIN/FREQ
10 MHz
66 MHz
MIN
TYP
3680
540
ps
MAX
UNIT
NOTE 8: tRNM represents the phase noise or jitter that the deserializer can withstand in the incoming data stream before bit errors occur.
timing diagrams and test circuits
TCLK
ODD DIN
EVEN DIN
Figure 2. Worst-Case Serializer I
CC
Test Pattern
SUPPLY CURRENT
vs
TCLK FREQUENCY
60
66 mA, 48.880 MHz
50
I CC 鈥?Supply Current 鈥?mA
40
ICC
30
20
10 mA, 14.732 MHz
10
0
0
20
40
60
80
TCLK Frequency 鈥?MHz
Figure 3.
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
11
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