SN65LV1023A/SN65LV1224A
10-MHz TO 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SLLS570A 鈥?JUNE 2003 鈥?REVISED JUNE 2003
timing diagrams and test circuits (continued)
1.2 V
RI
卤
VTH
VTL
1V
tDJIT
tRNM
tSW
Ideal Sampling Position
tSW: Setup and Hold Time (Internal Data Sampling Window)
tDJIT: Serializer Output Bit Position Jitter That Results From Jitter on TCLK
tRNM: Receiver Noise Margin Time
tDJIT
tRNM
Figure 18. Receiver LVDS Input Skew Margin
DO +
10
DIN
Parallel-to-Serial
DO 鈥?/div>
> TCLK
RL
VOD = (DO+) 鈥?(DO鈥?
Differential Output Signal Is Shown as (DO+) 鈥?(DO鈥?
Figure 19. V
OD
Diagram
18
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
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