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SN65LV1224A Datasheet

  • SN65LV1224A

  • 10-MHz TO 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER

  • 314.16KB

  • 22页

  • TI

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SN65LV1023A/SN65LV1224A
10-MHz TO 66-MHz, 10:1 LVDS SERIALIZER/DESERIALIZER
SLLS570A 鈥?JUNE 2003 鈥?REVISED JUNE 2003
APPLICATION INFORMATION
differential traces and termination
The performance of the SN65LV1023A/SN65LV1224A is affected by the characteristics of the transmission
medium. Use controlled-impedance media and termination at the receiving end of the transmission line with the
media鈥檚 characteristics impedance.
Use balanced cables such as twisted pair or differential traces that are ran close together. A balanced cable
picks up noise together and appears to the receiver as common mode. Differential receivers reject
common-mode noise. Keep cables or traces matched in length to help reduce skew.
Running the differential traces close together helps cancel the external magnetic field, as well as maintain a
constant impedance. Avoiding sharp turns and reducing the number of vias also helps.
topologies
There are several topologies that the serializers can operate. Three common examples are shown below.
Figure 20 shows an example of a single-terminated point-to-point connection. Here a single termination resistor
is located at the deserializer end. The resistor value should match that of the characteristic impedance of the
cable or PC board traces. The total load seen by the serializer is 100
鈩?
Double termination can be used and
typically reduces reflections compared with single termination. However, it also reduces the differential output
voltage swing.
AC-coupling is only recommended if the parallel TX data stream is encoded to achieve a dc-balanced data
stream. Otherwise the AC-caps can induce common mode voltage drift due to the dc-unbalanced data stream.
Serialized Data
Parallel Data In
100
鈩?/div>
Parallel Data Out
Figure 20. Single-Terminated Point-to-Point Connection
Figure 21 shows an example of a multidrop configuration. Here there is one transmitter broadcasting data to
multiple receivers. A 50-k鈩?resistor at the far end terminates the bus.
ASIC
ASIC
ASIC
ASIC
50
鈩?/div>
Figure 21. Multidrop Configuration
POST OFFICE BOX 655303
鈥?/div>
DALLAS, TEXAS 75265
19

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