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LPC2148FBD64 Datasheet

  • LPC2148FBD64

  • Single-chip 16-bit/32-bit microcontrollers; up to 512 kB fla...

  • 185.31KB

  • 38页

  • PHILIPS

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Philips Semiconductors
LPC2141/42/44/46/48
Single-chip 16-bit/32-bit microcontrollers
6. Functional description
6.1 Architectural overview
The ARM7TDMI-S is a general purpose 32-bit microprocessor, which offers high
performance and very low power consumption. The ARM architecture is based on
Reduced Instruction Set Computer (RISC) principles, and the instruction set and related
decode mechanism are much simpler than those of microprogrammed Complex
Instruction Set Computers (CISC). This simplicity results in a high instruction throughput
and impressive real-time interrupt response from a small and cost-effective processor
core.
Pipeline techniques are employed so that all parts of the processing and memory systems
can operate continuously. Typically, while one instruction is being executed, its successor
is being decoded, and a third instruction is being fetched from memory.
The ARM7TDMI-S processor also employs a unique architectural strategy known as
Thumb, which makes it ideally suited to high-volume applications with memory
restrictions, or applications where code density is an issue.
The key idea behind Thumb is that of a super-reduced instruction set. Essentially, the
ARM7TDMI-S processor has two instruction sets:
鈥?/div>
The standard 32-bit ARM set.
鈥?/div>
A 16-bit Thumb set.
The Thumb set鈥檚 16-bit instruction length allows it to approach twice the density of
standard ARM code while retaining most of the ARM鈥檚 performance advantage over a
traditional 16-bit processor using 16-bit registers. This is possible because Thumb code
operates on the same 32-bit register set as ARM code.
Thumb code is able to provide up to 65 % of the code size of ARM, and 160 % of the
performance of an equivalent ARM processor connected to a 16-bit memory system.
The particular 铿俛sh implementation in the LPC2141/42/44/46/48 allows for full speed
execution also in ARM mode. It is recommended to program performance critical and
short code sections (such as interrupt service routines and DSP algorithms) in ARM
mode. The impact on the overall code size will be minimal but the speed can be increased
by 30 % over Thumb mode.
6.2 On-chip 铿俛sh program memory
The LPC2141/42/44/46/48 incorporate a 32 kB, 64 kB, 128 kB, 256 kB and 512 kB 铿俛sh
memory system respectively. This memory may be used for both code and data storage.
Programming of the 铿俛sh memory may be accomplished in several ways. It may be
programmed In System via the serial port. The application program may also erase and/or
program the 铿俛sh while the application is running, allowing a great degree of 铿俥xibility for
data storage 铿乪ld 铿乺mware upgrades, etc. Due to the architectural solution chosen for an
on-chip boot loader, 铿俛sh memory available for user鈥檚 code on LPC2141/42/44/46/48 is
32 kB, 64 kB, 128 kB, 256 kB and 500 kB respectively.
The LPC2141/42/44/46/48 铿俛sh memory provides a minimum of 100,000 erase/write
cycles and 20 years of data-retention.
9397 750 14985
漏 Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Preliminary data sheet
Rev. 01 鈥?3 October 2005
12 of 38

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