MITSUBISHI MICROCOMPUTERS
3822 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
LCD Display RAM
Address 0040
16
to 004F
16
is the designated RAM for the LCD dis-
play. When 鈥?鈥?are written to these addresses, the corresponding
segments of the LCD display panel are turned on.
LCD Drive Timing
The LCDCK timing frequency (LCD drive timing) is generated in-
ternally and the frame frequency can be determined with the
following equation;
f(LCDCK) =
(frequency of count source for LCDCK)
(divider division ratio for LCD)
f(LCDCK)
(duty ratio)
Frame frequency =
B it
7
Address
6
5
SEG
1
SEG
3
SEG
5
SEG
7
SEG
9
SEG
11
SEG
13
SEG
15
SEG
17
SEG
19
SEG
21
SEG
23
SEG
25
SEG
27
SEG
29
SEG
31
4
3
2
1
SEG
0
SEG
2
SEG
4
SEG
6
SEG
8
SEG
10
SEG
12
SEG
14
SEG
16
SEG
18
SEG
20
SEG
22
SEG
24
SEG
26
SEG
28
SEG
30
0
0040
16
0041
16
0042
16
0043
16
0044
16
0045
16
0046
16
0047
16
0048
16
0049
16
004A
16
004B
16
004C
16
004D
16
004E
16
004F
16
COM
3
COM
2
COM
1
COM
0
COM
3
COM
2
COM
1
COM
0
Fig. 35 LCD display RAM map
37