level for 2 碌s or more. Then the RESET pin is returned to an 鈥淗鈥?/div>
level (the power source voltage should be between V
CC
(min.) and
5.5 V, and the quartz-crystal oscillator should be stable), reset is
released. After the reset is completed, the program starts from the
address contained in address FFFD
16
(high-order byte) and ad-
dress FFFC
16
(low-order byte). Make sure that the reset input
voltage meets V
IL
spec. when a power source voltage passes
V
CC
(min.).
Power on
Power
source
voltage
0V
Reset input
voltage
0V
V
IL
spec.
RESET
V
CC
RESET
V
CC
Power source voltage
detection circuit
Fig. 39 Reset Circuit Example
X
IN
蠁
RESET
Internal
reset
Reset address from
vector table
Address
Data
?
?
?
?
FFFC
AD
L
FFFD
AD
H,
AD
L
AD
H
SYNC
X
IN :
about 8000 cycles
Notes 1:
The frequency relation of f(X
IN
) and f(蠁) is f(X
IN
) =8鈥(蠁)
2:
The question marks (?) indicate an undefined state that depends on the previous state.
Fig. 40 Reset Sequence
41