1 Gb (8-Meg X 32-Bit X 4-Banks) SDRAM
C
URRENT
S
TATE
Write with auto-
precharge
CS
H
L
L
L
L
L
L
L
Refresh ( auto-
refresh)
H
L
L
L
L
L
L
RAS
x
H
H
H
L
L
L
L
x
H
H
H
L
L
L
CAS
x
H
L
L
H
H
L
L
x
H
L
L
H
H
L
WE
x
H
H
L
H
L
H
L
x
H
H
L
H
L
H
A
DDRESS
x
x
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
x
MODE
x
x
BA, CA, A10
BA, CA, A10
BA, RA
BA, A10
x
MODE
C
OMMAND
DESL
NOP
READ/READ A
WRIT/WRIT A
ACTV
PRE, PALL
REF, SELF
MRS
DESL
NOP
READ/READ A
WRIT/WRIT A
ACTV
PRE, PALL
REF, SELF
MRS
97SD3232
O
PERATION
Continue burst to end and pre-
charge
Continue burst to end and pre-
charge
ILLEGAL
1
ILLEGAL
1
Other bank active
ILLEGAL on same bank
4
ILLEGAL
1
ILLEGAL
ILLEGAL
Enter IDLE after t
RC
Enter IDLE after t
RC
ILLEGAL
3
ILLEGAL
3
ILLEGAL
3
ILLEGAL
3
ILLEGAL
ILLEGAL
Memory
L
L
L
L
1. Illegal for same bank, except for another bank
2. NOP for same bank, except for another bank
3. Illegal for all banks
4. If t
RRD
is not satisfied, this operation is illegal
5. An interval of t
DPL
is required between the final valid data input and the precharge command
From PRECHARGE state, command operation
To [DESL], [NOP]:
When these commands are executed, the SDRAM enters the IDLE state after t
RP
has
elapsed from the completion of precharge.
From IDLE state, command operation
To [DESL], [NOP], [PRE], or [PALL]:
These commands result in no operation.
To [ACTV]:
The bank specified by the address pins and the ROW address is activated.
To [REF], [SELF]:
The SDRAM enters refresh mode (auto-refresh or self-refresh).
To [MRS]:
The synchronous DRAM enters the mode register set cycle.
From ROW ACTIVE state, command operation
To [DESL], [NOP]:
These commands result in no operation.
To [READ], [READ A]:
A read operation starts. (However, an interval of t
RCD
is required.)
To [WRIT], [WRIT A]:
A write operation starts. (However, an interval of t
RCD
is required.)
01.11.05 Rev 2
All data sheets are subject to change without notice
14
漏2005 Maxwell Technologies
All rights reserved.