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97SD3232RPME Datasheet

  • 97SD3232RPME

  • 1 Gb SDRAM 8-Meg X 32 Bit X 4-Banks

  • 745.01KB

  • 39页

  • MAXWELL

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1 Gb (8-Meg X 32-Bit X 4-Banks) SDRAM
97SD3232
Mode register set to Bank-active interval:
The interval between setting the mode register and executing a
bank-active command must be no less than I
RSA
.
Memory
DQM Control
The DQM mask the bytes of the DQ data. The timing of DQM is different during reading and writing.
Reading:
When data is read, the output buffer can be controlled by DQM. By setting DQM to Low, the output
buffer becomes Low-Z, enabling data output. By setting DQM to High, the output buffer becomes High-Z and
the corresponding data is not output. However, internal reading operations continue. The latency of DQM
during reading is 2 clocks.
Writing:
Input data can be masked by DQM. By setting DQM to Low, data can be written. In addition, when
DQM is set to High, the corresponding data is not written, and previous data is held. The latency of DQM
during writing is 0 clock.
Reading
01.11.05 Rev 2
All data sheets are subject to change without notice
34
漏2005 Maxwell Technologies
All rights reserved.

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