您的位置：维库电子市场网 > Datasheet > DSPIC30F6011AT-20E/S

DSPIC30F6011AT-20E/S Datasheet

  • DSPIC30F6011AT-20E/S

  • High Performance Digital Signal Controllers

  • 3527.50KB

  • 222页

  • MICROCHIP   MICROCHIP

阅览下载 纠错 0

扫码查看芯片数据手册

上传产品规格书

PDF预览

dsPIC30F6011/6012/6013/6014
2.4.1
MULTIPLIER
2.4.2.1
The 17 x 17-bit multiplier is capable of signed or
unsigned operation and can multiplex its output using a
scaler to support either 1.31 fractional (Q31) or 32-bit
integer results. Unsigned operands are zero-extended
into the 17th bit of the multiplier input value. Signed
operands are sign-extended into the 17th bit of the mul-
tiplier input value. The output of the 17 x 17-bit multi-
plier/scaler is a 33-bit value which is sign-extended to
40 bits. Integer data is inherently represented as a
signed two鈥檚 complement value, where the MSB is
defined as a sign bit. Generally speaking, the range of
an N-bit two鈥檚 complement integer is -2
N-1
to 2
N-1
鈥?1.
For a 16-bit integer, the data range is -32768 (0x8000)
to 32767 (0x7FFF) including 鈥?鈥? For a 32-bit integer,
the data range is -2,147,483,648 (0x8000
0000)
to
2,147,483,645 (0x7FFF
FFFF).
When the multiplier is configured for fractional multipli-
cation, the data is represented as a two鈥檚 complement
fraction, where the MSB is defined as a sign bit and the
radix point is implied to lie just after the sign bit (QX for-
mat). The range of an N-bit two鈥檚 complement fraction
with this implied radix point is -1.0 to (1 鈥?2
1-N
). For a
16-bit fraction, the Q15 data range is -1.0 (0x8000) to
0.999969482 (0x7FFF) including 鈥?鈥?and has a preci-
sion of 3.01518x10
-5
. In Fractional mode, the 16x16
multiply operation generates a 1.31 product which has
a precision of 4.65661 x 10
-10
.
The same multiplier is used to support the MCU multi-
ply instructions which include integer 16-bit signed,
unsigned and mixed sign multiplies.
The
MUL
instruction may be directed to use byte or
word sized operands. Byte operands will direct a 16-bit
result, and word operands will direct a 32-bit result to
the specified register(s) in the W array.
Adder/Subtracter, Overflow and
Saturation
The adder/subtracter is a 40-bit adder with an optional
zero input into one side and either true, or complement
data into the other input. In the case of addition, the
carry/borrow input is active high and the other input is
true data (not complemented), whereas in the case of
subtraction, the carry/borrow input is active low and the
other input is complemented. The adder/subtracter
generates overflow status bits SA/SB and OA/OB,
which are latched and reflected in the STATUS register:
鈥?Overflow from bit 39: this is a catastrophic
overflow in which the sign of the accumulator is
destroyed.
鈥?Overflow into guard bits 32 through 39: this is a
recoverable overflow. This bit is set whenever all
the guard bits bits are not identical to each other.
The adder has an additional saturation block which
controls accumulator data saturation, if selected. It
uses the result of the adder, the overflow status bits
described above, and the SATA/B (CORCON<7:6>)
and ACCSAT (CORCON<4>) mode control bits to
determine when and to what value to saturate.
Six STATUS register bits have been provided to
support saturation and overflow; they are:
1.
2.
3.
OA:
AccA overflowed into guard bits
OB:
AccB overflowed into guard bits
SA:
AccA saturated (bit 31 overflow and saturation)
or
AccA overflowed into guard bits and saturated
(bit 39 overflow and saturation)
SB:
AccB saturated (bit 31 overflow and saturation)
or
AccB overflowed into guard bits and saturated
(bit 39 overflow and saturation)
OAB:
Logical OR of OA and OB
SAB:
Logical OR of SA and SB
2.4.2
DATA ACCUMULATORS AND
ADDER/SUBTRACTER
4.
The data accumulator consists of a 40-bit adder/
subtracter with automatic sign extension logic. It can
select one of two accumulators (A or B) as its pre-
accumulation source and post-accumulation destina-
tion. For the
ADD
and
LAC
instructions, the data to be
accumulated or loaded can be optionally scaled via the
barrel shifter, prior to accumulation.
5.
6.
The OA and OB bits are modified each time data
passes through the adder/subtracter. When set, they
indicate that the most recent operation has overflowed
into the accumulator guard bits (bits 32 through 39).
The OA and OB bits can also optionally generate an
arithmetic warning trap when set and the correspond-
ing overflow trap flag enable bit (OVATEN, OVBTEN) in
the INTCON1 register (refer to Section 5.0) is set. This
allows the user to take immediate action, for example,
to correct system gain.
铮?/div>
2004 Microchip Technology Inc.
Preliminary
DS70117C-page 19

DSPIC30F6011AT-20E/S相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

©2024 维库电子市场网（www.dzsc.com）　备案号：浙B2-20050339-1 经营许可证：浙B2-20210386版权声明
买家服务热线：0571-85317607 | 买家服务部QQ： QQ:1609526468
卖家服务热线：0571-85317607 | 卖家服务部QQ： QQ:331652727

扫码下载APP，
一键连接广大的电子世界。

在线人工客服

买家服务：
卖家服务：

0571-85317607

客服在线时间周一至周五
9:00-17:30

关注官方微信号，
第一时间获取资讯。

建议反馈
返回顶部

建议反馈

联系人：

联系方式：

按住滑块，拖拽到最右边
>>
感谢您向阿库提出的宝贵意见，您的参与是维库提升服务的动力！意见一经采纳，将有感恩红包奉上哦！

PDF纠错X

投诉电话：0571-85317607 投诉QQ：

如选匿名将无法为您反馈投诉结果，建议实名投诉！