您的位置：维库电子市场网 > Datasheet > DSPIC30F6011AT-20E/S

DSPIC30F6011AT-20E/S Datasheet

  • DSPIC30F6011AT-20E/S

  • High Performance Digital Signal Controllers

  • 3527.50KB

  • 222页

  • MICROCHIP   MICROCHIP

阅览下载 纠错 0

扫码查看芯片数据手册

上传产品规格书

PDF预览

dsPIC30F6011/6012/6013/6014
4.1.3
MOVE AND ACCUMULATOR
INSTRUCTIONS
In summary, the following Addressing modes are
supported by the
MAC
class of instructions:
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Register Indirect
Register Indirect Post-modified by 2
Register Indirect Post-modified by 4
Register Indirect Post-modified by 6
Register Indirect with Register Offset (Indexed)
Move instructions and the DSP accumulator class of
instructions provide a greater degree of addressing
flexibility than other instructions. In addition to the
Addressing modes supported by most MCU instruc-
tions, move and accumulator instructions also support
Register Indirect with Register Offset Addressing
mode, also referred to as Register Indexed mode.
Note:
For the
MOV
instructions, the Addressing
mode specified in the instruction can differ
for the source and destination EA.
However, the 4-bit Wb (register offset)
field is shared between both source and
destination (but typically only used by
one).
4.1.5
OTHER INSTRUCTIONS
In summary, the following Addressing modes are
supported by move and accumulator instructions:
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Register Direct
Register Indirect
Register Indirect Post-modified
Register Indirect Pre-modified
Register Indirect with Register Offset (Indexed)
Register Indirect with Literal Offset
8-bit Literal
16-bit Literal
Note:
Not all instructions support all the
Addressing modes given above. Individual
instructions may support different subsets
of these Addressing modes.
Besides the various Addressing modes outlined above,
some instructions use literal constants of various sizes.
For example,
BRA
(branch) instructions use 16-bit
signed literals to specify the branch destination directly,
whereas the
DISI
instruction uses a 14-bit unsigned
literal field. In some instructions, such as
ADD Acc,
the
source of an operand or result is implied by the opcode
itself. Certain operations, such as
NOP,
do not have any
operands.
4.2
Modulo Addressing
Modulo addressing is a method of providing an auto-
mated means to support circular data buffers using
hardware. The objective is to remove the need for soft-
ware to perform data address boundary checks when
executing tightly looped code, as is typical in many
DSP algorithms.
Modulo addressing can operate in either data or pro-
gram space (since the data pointer mechanism is
essentially the same for both). One circular buffer can
be supported in each of the X (which also provides the
pointers into program space) and Y data spaces. Mod-
ulo addressing can operate on any W register pointer.
However, it is not advisable to use W14 or W15 for mod-
ulo addressing since these two registers are used as
the stack frame pointer and stack pointer, respectively.
In general, any particular circular buffer can only be
configured to operate in one direction, as there are cer-
tain restrictions on the buffer start address (for incre-
menting buffers), or end address (for decrementing
buffers) based upon the direction of the buffer.
The only exception to the usage restrictions is for buff-
ers which have a power-of-2 length. As these buffers
satisfy the start and end address criteria, they may
operate in a Bidirectional mode (i.e., address boundary
checks will be performed on both the lower and upper
address boundaries).
4.1.4
MAC
INSTRUCTIONS
The dual source operand DSP instructions (CLR,
ED,
EDAC, MAC, MPY, MPY.N, MOVSAC
and
MSC),
also
referred to as
MAC
instructions, utilize a simplified set of
Addressing modes to allow the user to effectively
manipulate the data pointers through register indirect
tables.
The 2 source operand pre-fetch registers must be a
member of the set {W8, W9, W10, W11}. For data
reads, W8 and W9 will always be directed to the X
RAGU and W10 and W11 will always be directed to the
Y AGU. The effective addresses generated (before and
after modification) must, therefore, be valid addresses
within X data space for W8 and W9 and Y data space
for W10 and W11.
Note:
Register indirect with register offset
addressing is only available for W9 (in X
space) and W11 (in Y space).
DS70117C-page 38
Preliminary
铮?/div>
2004 Microchip Technology Inc.

DSPIC30F6011AT-20E/S相关型号PDF文件下载

您可能感兴趣的PDF文件资料

热门IC型号推荐

©2024 维库电子市场网（www.dzsc.com）　备案号：浙B2-20050339-1 经营许可证：浙B2-20210386版权声明
买家服务热线：0571-85317607 | 买家服务部QQ： QQ:1609526468
卖家服务热线：0571-85317607 | 卖家服务部QQ： QQ:331652727

扫码下载APP，
一键连接广大的电子世界。

在线人工客服

买家服务：
卖家服务：

0571-85317607

客服在线时间周一至周五
9:00-17:30

关注官方微信号，
第一时间获取资讯。

建议反馈
返回顶部

建议反馈

联系人：

联系方式：

按住滑块，拖拽到最右边
>>
感谢您向阿库提出的宝贵意见，您的参与是维库提升服务的动力！意见一经采纳，将有感恩红包奉上哦！

PDF纠错X

投诉电话：0571-85317607 投诉QQ：

如选匿名将无法为您反馈投诉结果，建议实名投诉！