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DSPIC30F6011AT-20E/S Datasheet

  • DSPIC30F6011AT-20E/S

  • High Performance Digital Signal Controllers

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  • MICROCHIP   MICROCHIP

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dsPIC30F6011/6012/6013/6014
7.3
Writing to the Data EEPROM
To write an EEPROM data location, the following
sequence must be followed:
1.
Erase data EEPROM word.
a) Select word, data EEPROM erase, and set
WREN bit in NVMCON register.
b) Write address of word to be erased into
NVMADR.
c) Enable NVM interrupt (optional).
d) Write 鈥?5鈥?to NVMKEY.
e) Write 鈥楢A鈥?to NVMKEY.
f) Set the WR bit. This will begin erase cycle.
g) Either poll NVMIF bit or wait for NVMIF
interrupt.
h) The WR bit is cleared when the erase cycle
ends.
Write data word into data EEPROM write
latches.
Program 1 data word into data EEPROM.
a) Select word, data EEPROM program, and
set WREN bit in NVMCON register.
b) Enable NVM write done interrupt (optional).
c) Write 鈥?5鈥?to NVMKEY.
d) Write 鈥楢A鈥?to NVMKEY.
e) Set the WR bit. This will begin program
cycle.
f) Either poll NVMIF bit or wait for NVM
interrupt.
g) The WR bit is cleared when the write cycle
ends.
The write will not initiate if the above sequence is not
exactly followed (write
0x55
to NVMKEY, write
0xAA
to
NVMCON, then set WR bit) for each word. It is strongly
recommended that interrupts be disabled during this
code segment.
Additionally, the WREN bit in NVMCON must be set to
enable writes. This mechanism prevents accidental
writes to data EEPROM due to unexpected code exe-
cution. The WREN bit should be kept clear at all times
except when updating the EEPROM. The WREN bit is
not cleared by hardware.
After a write sequence has been initiated, clearing the
WREN bit will not affect the current write cycle. The WR
bit will be inhibited from being set unless the WREN bit
is set. The WREN bit must be set on a previous instruc-
tion. Both WR and WREN cannot be set with the same
instruction.
At the completion of the write cycle, the WR bit is
cleared in hardware and the Non-Volatile Memory
Write Complete Interrupt Flag bit (NVMIF) is set. The
user may either enable this interrupt or poll this bit.
NVMIF must be cleared by software.
2.
3.
7.3.1
WRITING A WORD OF DATA
EEPROM
Once the user has erased the word to be programmed,
then a table write instruction is used to write one write
latch, as shown in Example 7-4.
EXAMPLE 7-4:
DATA EEPROM WORD WRITE
; Init pointer
; Point to data memory
MOV
#LOW_ADDR_WORD,W0
MOV
#HIGH_ADDR_WORD,W1
MOV
W1
,
TBLPAG
MOV
#LOW(WORD),W2
TBLWTL
W2
,
[ W0]
; The NVMADR captures last table access address
; Select data EEPROM for 1 word op
MOV
#0x4004,W0
MOV
W0
,
NVMCON
; Operate key to allow write operation
DISI
#5
; Get data
; Write data
; Block all interrupts with priority <7 for
; next 5 instructions
MOV
#0x55,W0
; Write the 0x55 key
MOV
W0
,
NVMKEY
MOV
#0xAA,W1
; Write the 0xAA key
MOV
W1
,
NVMKEY
BSET
NVMCON,#WR
; Initiate program sequence
NOP
NOP
; Write cycle will complete in 2mS. CPU is not stalled for the Data Write Cycle
; User can poll WR bit, use NVMIF or Timer IRQ to determine write complete
铮?/div>
2004 Microchip Technology Inc.
Preliminary
DS70117C-page 57

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