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DSPIC30F6011AT-20E/S Datasheet

  • DSPIC30F6011AT-20E/S

  • High Performance Digital Signal Controllers

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  • MICROCHIP   MICROCHIP

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dsPIC30F6011/6012/6013/6014
13.0
OUTPUT COMPARE MODULE
This section describes the output compare module and
associated Operational modes. The features provided
by this module are useful in applications requiring
Operational modes, such as:
鈥?Generation of Variable Width Output Pulses
鈥?Power Factor Correction
Figure 13-1 depicts a block diagram of the output
compare module.
The key operational features of the output compare
module include:
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
鈥?/div>
Timer2 and Timer3 Selection mode
Simple Output Compare Match mode
Dual Output Compare Match mode
Simple PWM mode
Output Compare During Sleep and Idle modes
Interrupt on Output Compare/PWM Event
These Operating modes are determined by setting the
appropriate bits in the 16-bit OCxCON SFR (where
x = 1,2,3,...,N). The dsPIC devices contain up to 8
compare channels (i.e., the maximum value of N is 8).
OCxRS and OCxR in Figure 13-1 represent the Dual
Compare registers. In the Dual Compare mode, the
OCxR register is used for the first compare and OCxRS
is used for the second compare.
FIGURE 13-1:
OUTPUT COMPARE MODE BLOCK DIAGRAM
Set Flag bit
OCxIF
OCxRS
OCxR
Output
Logic
3
S Q
R
Output
Enable
OCx
Comparator
OCTSEL
OCM<2:0>
Mode Select
OCFA
(for x = 1, 2, 3 or 4)
or OCFB
(for x = 5, 6, 7 or 8)
0
1
0
1
From GP
Timer Module
TMR2<15:0
TMR3<15:0> T2P2_MATCH
T3P3_MATCH
Note:
Where 鈥榵鈥?is shown, reference is made to the registers associated with the respective output compare
channels 1 through N.
铮?/div>
2004 Microchip Technology Inc.
Preliminary
DS70117C-page 85

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