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H8/3690 Datasheet

  • H8/3690

  • 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Seri...

  • 2454.14KB

  • 432页

  • RENESAS

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Section 16
Figure 16.1
Figure 16.2
Figure 16.3
Figure 16.4
Figure 16.5
Figure 16.6
Section 17
Figure 17.1
Figure 17.2
Figure 17.3
Figure 17.4
Figure 17.5
Figure 17.6
Figure 17.7
Section 18
Figure 18.1
Figure 18.2
Figure 18.3
Figure 18.4
Figure 18.5
A/D Converter
Block Diagram of A/D Converter ........................................................................... 252
A/D Conversion Timing .......................................................................................... 258
External Trigger Input Timing ................................................................................ 259
A/D Conversion Accuracy Definitions (1) .............................................................. 260
A/D Conversion Accuracy Definitions (2) .............................................................. 261
Analog Input Circuit Example................................................................................. 262
EEPROM
Block Diagram of EEPROM ................................................................................... 264
EEPROM Bus Format and Bus Timing .................................................................. 266
Byte Write Operation .............................................................................................. 269
Page Write Operation .............................................................................................. 269
Current Address Read Operation............................................................................. 271
Random Address Read Operation ........................................................................... 271
Sequential Read Operation (when current address read is used)............................. 272
Power-On Reset and Low-Voltage Detection Circuits (Optional)
Block Diagram of Power-On Reset Circuit and Low-Voltage Detection Circuit.... 276
Operational Timing of Power-On Reset Circuit...................................................... 279
Operational Timing of LVDR Circuit ..................................................................... 280
Operational Timing of LVDI Circuit....................................................................... 281
Timing for Operation/Release of Low-Voltage Detection Circuit .......................... 282
Section 19 Power Supply Circuit
Figure 19.1 Power Supply Connection when Internal Step-Down Circuit is Used .................... 283
Figure 19.2 Power Supply Connection when Internal Step-Down Circuit is Not Used ............. 284
Section 21
Figure 21.1
Figure 21.2
Figure 21.3
Figure 21.4
Figure 21.5
Figure 21.6
Figure 21.7
Figure 21.8
Electrical Characteristics
System Clock Input Timing..................................................................................... 331
RES
Low Width Timing.......................................................................................... 331
Input Timing............................................................................................................ 331
I
2
C Bus Interface Input/Output Timing ................................................................... 332
SCK3 Input Clock Timing....................................................................................... 332
SCI Input/Output Timing in Clocked Synchronous Mode ...................................... 333
EEPROM Bus Timing............................................................................................. 333
Output Load Circuit................................................................................................. 334
Appendix B I/O Port Block Diagrams
Figure B.1 Port 1 Block Diagram (P17) ..................................................................................... 365
Figure B.2 Port 1 Block Diagram (P16 to P14) .......................................................................... 366
Figure B.3 Port 1 Block Diagram (P12, P11) ............................................................................. 367
Figure B.4 Port 1 Block Diagram (P10) ..................................................................................... 368
Figure B.5 Port 2 Block Diagram (P22) ..................................................................................... 369
Figure B.6 Port 2 Block Diagram (P21) ..................................................................................... 370
Rev. 4.00, 03/04, page xxiii of xxviii

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