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H8/3690 Datasheet

  • H8/3690

  • 16-Bit Single-Chip Microcomputer H8 Family/H8/300H Tiny Seri...

  • 2454.14KB

  • 432页

  • RENESAS

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Section 3 Exception Handling
Exception handling may be caused by a reset, a trap instruction (TRAPA), or interrupts.
鈥?/div>
Reset
A reset has the highest exception priority. Exception handling starts as soon as the reset is cleared
by the
RES
pin. The chip is also reset when the watchdog timer overflows, and exception handling
starts. Exception handling is the same as exception handling by the
RES
pin.
鈥?/div>
Trap Instruction
Exception handling starts when a trap instruction (TRAPA) is executed. The TRAPA instruction
generates a vector address corresponding to a vector number from 0 to 3, as specified in the
instruction code. Exception handling can be executed at all times in the program execution state,
regardless of the setting of the I bit in CCR.
鈥?/div>
Interrupts
External interrupts other than NMI and internal interrupts other than address break are masked by
the I bit in CCR, and kept masked while the I bit is set to 1. Exception handling starts when the
current instruction or exception handling ends, if an interrupt request has been issued.
3.1
Exception Sources and Vector Address
Table 3.1 shows the vector addresses and priority of each exception handling. When more than
one interrupt is requested, handling is performed from the interrupt with the highest priority.
Table 3.1
Exception Sources and Vector Address
Exception Sources
Reset
Reserved for system use
Vector
Number
0
1 to 6
7
8
9
10
11
12
13
Vector Address
H'0000 to H'0001
H'0002 to H'000D
H'000E to H'000F
H'0010 to H'0011
H'0012 to H'0013
H'0014 to H'0015
H'0016 to H'0017
H'0018 to H'0019
H'001A to H'001B
Low
Priority
High
Relative Module
RES
pin
Watchdog timer
铮?/div>
CPU
External interrupt pin NMI
Trap instruction (#0)
(#1)
(#2)
(#3)
Address break
CPU
Break conditions satisfied
Direct transition by executing
the SLEEP instruction
Rev. 4.00, 03/04, page 47 of 400

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