鈥?/div>
Interrupt edge select register 1 (IEGR1)
Interrupt edge select register 2 (IEGR2)
Interrupt enable register 1 (IENR1)
Interrupt flag register 1 (IRR1)
Wakeup interrupt flag register (IWPR)
Interrupt Edge Select Register 1 (IEGR1)
3.2.1
IEGR1 selects the direction of an edge that generates interrupt requests of pins
NMI
and
IRQ3
to
IRQ0.
Bit
7
Bit Name
NMIEG
Initial
Value
0
R/W
R/W
Description
NMI Edge Select
0: Falling edge of
NMI
pin input is detected
1: Rising edge of
NMI
pin input is detected
6 to 4
3
铮?/div>
IEG3
All 1
0
铮?/div>
R/W
Reserved
These bits are always read as 1.
IRQ3 Edge Select
0: Falling edge of
IRQ3
pin input is detected
1: Rising edge of
IRQ3
pin input is detected
2
IEG2
0
R/W
IRQ2 Edge Select
0: Falling edge of
IRQ2
pin input is detected
1: Rising edge of
IRQ2
pin input is detected
1
IEG1
0
R/W
IRQ1 Edge Select
0: Falling edge of
IRQ1
pin input is detected
1: Rising edge of
IRQ1
pin input is detected
0
IEG0
0
R/W
IRQ0 Edge Select
0: Falling edge of
IRQ0
pin input is detected
1: Rising edge of
IRQ0
pin input is detected
Rev. 4.00, 03/04, page 49 of 400
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