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EDX5116ABSE-3B-E Datasheet

  • EDX5116ABSE-3B-E

  • 512M bits XDR DRAM (32M words ?16 bits)

  • 3580.77KB

  • 78页

  • ELPIDA

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EDX5116ABSE
Timing Conditions
Table 13 summarizes all timing conditions that may be applied
to the memory component. The first section of parameters is
concerned with parameters for the clock signals. The second
section of parameters is concerned with parameters for the
request signals. The third section of parameters is concerned
Table 13
Timing
Symbol
t
CYCLE
or t
CYC,CFM
Parameter and Other Conditions
CFM RSL clock - cycle time
-4000
-3200
-2400
with parameters for the write data signals. The fourth section
of parameters is concerned with parameters for the serial inter-
face signals. The fifth section is concerned with all other
parameters, including those for refresh, calibration, power state
transitions, and initialization.
Conditions
Minimum
2.000
2.500
3.333
0.080
40%
0.080
0.170
0.200
0.275
0.020
0.052
0.065
0.080
-0.080
20
-
40%
-
5
10
Maximum
3.830
3.830
3.830
0.200
60%
0.260
-
-
-
0.074
-
-
-
+0.080
-
5.0
60%
5.0
-
-
ns
ns
ns
t
CYCLE
t
CYCLE
t
CYCLE
ns
ns
ns
t
CYCLE
ns
ns
ns
t
CYCLE
ns
ns
t
CYC,SCK
ns
ns
t
CYC,SCK
Units
Figure(s)
Figure 48
t
R,CFM
, t
F,CFM
t
H,CFM
, t
L,CFM
t
R,RQ
, t
F,RQ
t
S,RQ
, t
H,RQ
CFM/CFMN input - rise and fall time - use minimum for test.
CFM/CFMN input - high and low times
RSL RQ input - rise/fall times (20% - 80%) - use minimum for test.
RSL RQ input to sample points
(set/hold)
@ 2.500 ns
>
t
CYCLE
鈮?/div>
2.000 ns
@ 3.333 ns
>
t
CYCLE
鈮?/div>
2.500 ns
@ 3.830 ns
鈮?/div>
t
CYCLE
鈮?/div>
3.333 ns
Figure 48
Figure 48
Figure 49
Figure 49
t
IR,DQ
, t
IF,DQ
t
S,DQ
, t
H,DQ
DRSL DQ input - rise/fall times (20% - 80%) - use minimum for test.
DRSL DQ input to sample points
(set/hold)
@ 2.500 ns
>
t
CYCLE
鈮?/div>
2.000 ns
@ 3.333 ns
>
t
CYCLE
鈮?/div>
2.500 ns
@ 3.830 ns
鈮?/div>
t
CYCLE
鈮?/div>
3.333 ns
Figure 50
Figure 50
t
DOFF,DQ
t
CYC,SCK
t
R,SCK,
t
F,SCK
t
H,SCK
, t
L,SCK
t
IR,SI,
t
IF,SI
t
S,SI
,t
H,SI
t
DLY,SI-RQ
DRSL DQ input delay offset (fixed) to sample points
Serial Interface SCK input - cycle time
Serial Interface SCK input - rise and fall times
Serial Interface SCK input - high and low times
Serial Interface CMD,RST,SDI input - rise and fall times
Serial Interface CMD,SDI input to SCK clock edge - set/hold time
Delay from last SCK clock edge for register operation to first CFM edge with
RQ packet. Also, delay from first CFM edge with RQ packet to the first SCK
clock edge for register operation.
Refresh interval. Every row of every bank must be accessed at least once in this
interval with a ROW-ACT, ROWP-REF or ROWP-REFI command.
Average refresh command interval. ROWP-REFA or ROWP-REFI commands
must be issued at this average rate. This depends upon t
REF
and the number of
banks and rows: t
REFA-REFA,AVG
= t
REF
/(N
B
*N
R
) = t
REF
/(2
3
*2
12
).
Refresh burst limit. The number of ROWP-REFA or ROWP-REFI commands
which can be issued consecutively at the minimum command spacing.
Refresh burst interval. The interval between a burst of N
REFA,BURST,MAX
ROWP-REFA or ROWP-REFI commands and the next ROWP-REFA or
ROWP-REFI command.
Interval needed for core initialialization after power is applied.
Current calibration interval
Delay between packet with any command
and CALC/CALZ packet
w/ PRE or REFP command
w/ any other command
Figure 50
Figure 52
Figure 52
Figure 52
Figure 52
Figure 52
-
t
REF
t
REFA-REFA,AVG
-
16
t
REFA-REFA,AVG
= 488
ms
ns
Figure 34
-
N
REFA,BURST
t
BURST-REFA
-
40
128
-
commands
t
CYCLE
-
-
t
COREINIT
t
CALC,
t
CALZ
t
CMD-CALC
, t
CMD-CALZ
,
t
CALCE
, t
CALZE
-
-
4
16
12
1.500
100
-
-
-
ms
ms
t
CYCLE
t
CYCLE
-
Figure 35
Figure 35
Figure 35
Delay between CALC/CALZ packet and CALE packet
Preliminary Data Sheet E0643E30 (Ver. 3.0)
59

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