ST7232AK1B1 Datasheet

IC型号：
ST7232AK1B1
PDF描述：
8-BIT MCU WITH 8K FLASH/ROM, ADC, 4 TIMERS, SPI, SCI INTERFA...
文件大小：
1290.53KB
PDF页数：
154页
芯片厂家：
STMICROELECTRONICS

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ST7232A

7 INTERRUPTS

7.1 INTRODUCTION

The ST7 enhanced interrupt management pro-

vides the following features:

鈻?/div>

Hardware interrupts

鈻?/div>

Software interrupt (TRAP)

鈻?/div>

Nested or concurrent interrupt management

with flexible interrupt priority and level

management:

鈥?Up to 4 software programmable nesting levels

鈥?Up to 16 interrupt vectors fixed by hardware

鈥?2 non maskable events: RESET, TRAP

This interrupt management is based on:

鈥?Bit 5 and bit 3 of the CPU CC register (I1:0),

鈥?Interrupt software priority registers (ISPRx),

鈥?Fixed interrupt vector addresses located at the

high addresses of the memory map (FFE0h to

FFFFh) sorted by hardware priority order.

This enhanced interrupt controller guarantees full

upward compatibility with the standard (not nest-

ed) ST7 interrupt controller.

7.2 MASKING AND PROCESSING FLOW

The interrupt masking is managed by the I1 and I0

bits of the CC register and the ISPRx registers

which give the interrupt software priority level of

each interrupt vector (see

Table 6).

The process-

ing flow is shown in

Figure 14

Figure 14. Interrupt Processing Flowchart

RESET

PENDING

INTERRUPT

TRAP

Interrupt has the same or a

lower software priority

than current one

I1:0

Interrupt has a higher

software priority

than current one

When an interrupt request has to be serviced:

鈥?Normal processing is suspended at the end of

the current instruction execution.

鈥?The PC, X, A and CC registers are saved onto

the stack.

鈥?I1 and I0 bits of CC register are set according to

the corresponding values in the ISPRx registers

of the serviced interrupt vector.

鈥?The PC is then loaded with the interrupt vector of

the interrupt to service and the first instruction of

the interrupt service routine is fetched (refer to

鈥淚nterrupt Mapping鈥?table for vector addresses).

The interrupt service routine should end with the

IRET instruction which causes the contents of the

saved registers to be recovered from the stack.

Note:

As a consequence of the IRET instruction,

the I1 and I0 bits will be restored from the stack

and the program in the previous level will resume.

Table 6. Interrupt Software Priority Levels

Interrupt software priority

Level 0 (main)

Level 1

Level 2

Level 3 (= interrupt disable)

Level

Low

High

FETCH NEXT

INSTRUCTION

THE INTERRUPT

STAYS PENDING

鈥淚RET鈥?/div>

RESTORE PC, X, A, CC

FROM STACK

EXECUTE

INSTRUCTION

STACK PC, X, A, CC

LOAD I1:0 FROM INTERRUPT SW REG.

LOAD PC FROM INTERRUPT VECTOR

26/154

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