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ST7232AK1B1 Datasheet

  • ST7232AK1B1

  • 8-BIT MCU WITH 8K FLASH/ROM, ADC, 4 TIMERS, SPI, SCI INTERFA...

  • 1290.53KB

  • 154页

  • STMICROELECTRONICS   STMICROELECTRONICS

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ST7232A
SERIAL PERIPHERAL INTERFACE
(Cont鈥檇)
鈥?SS: Slave select:
This input signal acts as a 鈥榗hip select鈥?to let
the SPI master communicate with slaves indi-
vidually and to avoid contention on the data
lines. Slave SS inputs can be driven by stand-
ard I/O ports on the master MCU.
10.4.3.1 Functional Description
A basic example of interconnections between a
single master and a single slave is illustrated in
Figure 44.
The MOSI pins are connected together and the
MISO pins are connected together. In this way
data is transferred serially between master and
slave (most significant bit first).
Figure 44. Single Master/ Single Slave Application
The communication is always initiated by the mas-
ter. When the master device transmits data to a
slave device via MOSI pin, the slave device re-
sponds by sending data to the master device via
the MISO pin. This implies full duplex communica-
tion with both data out and data in synchronized
with the same clock signal (which is provided by
the master device via the SCK pin).
To use a single data line, the MISO and MOSI pins
must be connected at each node ( in this case only
simplex communication is possible).
Four possible data/clock timing relationships may
be chosen (see
Figure 47)
but master and slave
must be programmed with the same timing mode.
MASTER
MSBit
LSBit
MISO
MISO
MSBit
SLAVE
LSBit
8-BIT SHIFT REGISTER
8-BIT SHIFT REGISTER
MOSI
MOSI
SPI
CLOCK
GENERATOR
SCK
SS
+5V
SCK
SS
Not used if SS is managed
by software
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