ST7232AK1B1 Datasheet

IC型号：
ST7232AK1B1
PDF描述：
8-BIT MCU WITH 8K FLASH/ROM, ADC, 4 TIMERS, SPI, SCI INTERFA...
文件大小：
1290.53KB
PDF页数：
154页
芯片厂家：
STMICROELECTRONICS

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ST7232A

10 ON-CHIP PERIPHERALS

10.1 WATCHDOG TIMER (WDG)

10.1.1 Introduction

The Watchdog timer is used to detect the occur-

rence of a software fault, usually generated by ex-

ternal interference or by unforeseen logical condi-

tions, which causes the application program to

abandon its normal sequence. The Watchdog cir-

cuit generates an MCU reset on expiry of a pro-

grammed time period, unless the program refresh-

es the counter鈥檚 contents before the T6 bit be-

comes cleared.

10.1.2 Main Features

鈻?/div>

Programmable free-running downcounter

鈻?/div>

Programmable reset

鈻?/div>

Reset (if watchdog activated) when the T6 bit

reaches zero

鈻?/div>

Optional

reset

HALT

instruction

(configurable by option byte)

鈻?/div>

Hardware Watchdog selectable by option byte

10.1.3 Functional Description

The counter value stored in the Watchdog Control

every 16384 f

OSC2

cycles (approx.), and the

length of the timeout period can be programmed

by the user in 64 increments.

If the watchdog is activated (the WDGA bit is set)

and when the 7-bit timer (bits T[6:0]) rolls over

from 40h to 3Fh (T6 becomes cleared), it initiates

a reset cycle pulling low the reset pin for typically

500ns.

The application program must write in the

WDGCR register at regular intervals during normal

operation to prevent an MCU reset. This down-

counter is free-running: it counts down even if the

watchdog is disabled. The value to be stored in the

WDGCR register must be between FFh and C0h:

鈥?The WDGA bit is set (watchdog enabled)

鈥?The T6 bit is set to prevent generating an imme-

diate reset

鈥?The T[5:0] bits contain the number of increments

which represents the time delay before the

watchdog produces a reset (see

Figure 29. Ap-

proximate Timeout Duration).

The timing varies

between a minimum and a maximum value due

to the unknown status of the prescaler when writ-

ing to the WDGCR register (see

Figure 30).

Following a reset, the watchdog is disabled. Once

activated it cannot be disabled, except by a reset.

The T6 bit can be used to generate a software re-

set (the WDGA bit is set and the T6 bit is cleared).

If the watchdog is activated, the HALT instruction

will generate a Reset.

Figure 28. Watchdog Block Diagram

RESET

OSC2

MCC/RTC

WATCHDOG CONTROL REGISTER (WDGCR)

DIV 64

WDGA

6-BIT DOWNCOUNTER (CNT)

12-BIT MCC

RTC COUNTER

MSB

6 5

LSB

TB[1:0] bits

(MCCSR

WDG PRESCALER

DIV 4

46/154

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