鈻?/div>
5 alternate functions on I/O ports (ICAP1, ICAP2,
OCMP1, OCMP2, EXTCLK)*
The Block Diagram is shown in
Figure 32.
*Note:
Some timer pins may not be available (not
bonded) in some ST7 devices. Refer to the device
pin out description.
When reading an input signal on a non-bonded
pin, the value will always be 鈥?鈥?
10.3.3 Functional Description
10.3.3.1 Counter
The main block of the Programmable Timer is a
16-bit free running upcounter and its associated
16-bit registers. The 16-bit registers are made up
of two 8-bit registers called high & low.
Counter Register (CR):
鈥?Counter High Register (CHR) is the most sig-
nificant byte (MS Byte).
鈥?Counter Low Register (CLR) is the least sig-
nificant byte (LS Byte).
Alternate Counter Register (ACR)
鈥?Alternate Counter High Register (ACHR) is
the most significant byte (MS Byte).
鈥?Alternate Counter Low Register (ACLR) is the
least significant byte (LS Byte).
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Status register, (SR),
(see note at the end of paragraph titled 16-bit read
sequence).
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
Both counters have a reset value of FFFCh (this is
the only value which is reloaded in the 16-bit tim-
er). The reset value of both counters is also
FFFCh in One Pulse mode and PWM mode.
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in
Table 16 Clock
Control Bits.
The value in the counter register re-
peats every 131072, 262144 or 524288 CPU clock
cycles depending on the CC[1:0] bits.
The timer frequency can be f
CPU
/2, f
CPU
/4, f
CPU
/8
or an external frequency.
Caution:
In Flash devices, Timer A functionality
has the following restrictions:
鈥?TAOC2HR and TAOC2LR registers are write
only
鈥?Input Capture 2 is not implemented
鈥?The corresponding interrupts cannot be used
(ICF2, OCF2 forced by hardware to zero)
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